A high speed Sorting Processor ASIC for the RPC Trigger system of the CMS experiment

The design of a high speed Sorting Processor ASIC is presented. It was designed in BiCMOS 0.8 mu m technology and its aim is to reorder and provide the four highest words among eight input words, in decreasing order. This chip is the main component of the sorting tree of the Trigger Muon System of t...

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Detalles Bibliográficos
Autores principales: De Robertis, G, Loddo, F, Ranieri, A
Lenguaje:eng
Publicado: 1999
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.1016/S0168-9002(99)00470-2
http://cds.cern.ch/record/781165
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author De Robertis, G
Loddo, F
Ranieri, A
author_facet De Robertis, G
Loddo, F
Ranieri, A
author_sort De Robertis, G
collection CERN
description The design of a high speed Sorting Processor ASIC is presented. It was designed in BiCMOS 0.8 mu m technology and its aim is to reorder and provide the four highest words among eight input words, in decreasing order. This chip is the main component of the sorting tree of the Trigger Muon System of the CMS experiment.
id cern-781165
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 1999
record_format invenio
spelling cern-7811652019-09-30T06:29:59Zdoi:10.1016/S0168-9002(99)00470-2http://cds.cern.ch/record/781165engDe Robertis, GLoddo, FRanieri, AA high speed Sorting Processor ASIC for the RPC Trigger system of the CMS experimentDetectors and Experimental TechniquesThe design of a high speed Sorting Processor ASIC is presented. It was designed in BiCMOS 0.8 mu m technology and its aim is to reorder and provide the four highest words among eight input words, in decreasing order. This chip is the main component of the sorting tree of the Trigger Muon System of the CMS experiment.oai:cds.cern.ch:7811651999
spellingShingle Detectors and Experimental Techniques
De Robertis, G
Loddo, F
Ranieri, A
A high speed Sorting Processor ASIC for the RPC Trigger system of the CMS experiment
title A high speed Sorting Processor ASIC for the RPC Trigger system of the CMS experiment
title_full A high speed Sorting Processor ASIC for the RPC Trigger system of the CMS experiment
title_fullStr A high speed Sorting Processor ASIC for the RPC Trigger system of the CMS experiment
title_full_unstemmed A high speed Sorting Processor ASIC for the RPC Trigger system of the CMS experiment
title_short A high speed Sorting Processor ASIC for the RPC Trigger system of the CMS experiment
title_sort high speed sorting processor asic for the rpc trigger system of the cms experiment
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.1016/S0168-9002(99)00470-2
http://cds.cern.ch/record/781165
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