Cargando…
A high speed Sorting Processor ASIC for the RPC Trigger system of the CMS experiment
The design of a high speed Sorting Processor ASIC is presented. It was designed in BiCMOS 0.8 mu m technology and its aim is to reorder and provide the four highest words among eight input words, in decreasing order. This chip is the main component of the sorting tree of the Trigger Muon System of t...
| Autores principales: | , , |
|---|---|
| Lenguaje: | eng |
| Publicado: |
1999
|
| Materias: | |
| Acceso en línea: | https://dx.doi.org/10.1016/S0168-9002(99)00470-2 http://cds.cern.ch/record/781165 |