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TTC Interface Module for ATLAS Read-Out Electronics: Final production version based on Xilinx FPGA devices
The functionality and the details of firmware, software and hardware of the Xilinx FPGA-based production version of the ATLAS-SCT TTC Interface Module ( TIM ) are described. The TIM interfaces to the ATLAS Level-1 Trigger, using the LHC-standard TTC ( Timing, Trigger and Control ) system. Twelve pro...
Autores principales: | , , , |
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Lenguaje: | eng |
Publicado: |
CERN
2004
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Materias: | |
Acceso en línea: | https://dx.doi.org/10.5170/CERN-2004-010.320 http://cds.cern.ch/record/814349 |
Sumario: | The functionality and the details of firmware, software and hardware of the Xilinx FPGA-based production version of the ATLAS-SCT TTC Interface Module ( TIM ) are described. The TIM interfaces to the ATLAS Level-1 Trigger, using the LHC-standard TTC ( Timing, Trigger and Control ) system. Twelve prototype TIM modules have been built and used since 2001, based around ten AMD/Lattice CPLD devices. Final production modules, based on two Xilinx FPGAs, are all being built this year. The details of the hardware and firmware transition from CPLD to FPGA version are described, including the use of new software tools. |
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