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Design and implementation for static Huffman encoding hardware with parallel shifting algorithm
This paper presents an implementation of static Huffman encoding hardware for real-time lossless compression in the ECAL of the CMS detector. The construction of the Huffman encoding hardware shows an implementation for optimizing its logic size. The number of logic gates of the parallel shift opera...
Autores principales: | , |
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Lenguaje: | eng |
Publicado: |
2004
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Materias: | |
Acceso en línea: | http://cds.cern.ch/record/818308 |
_version_ | 1780905463930421248 |
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author | Tae Yeon Lee Jae Hong Park |
author_facet | Tae Yeon Lee Jae Hong Park |
author_sort | Tae Yeon Lee |
collection | CERN |
description | This paper presents an implementation of static Huffman encoding hardware for real-time lossless compression in the ECAL of the CMS detector. The construction of the Huffman encoding hardware shows an implementation for optimizing its logic size. The number of logic gates of the parallel shift operation for the hardware is analyzed. Two kinds of implementation methods of the parallel shift operation are compared in aspect of logic size. The experiment with the hardware on a simulated ECAL environment covering 99.9999% of original distribution shows promising result with the simulation that the compression rate was 4.0039 and the maximum length of the stored data in the input buffer was 44. (14 refs). |
id | cern-818308 |
institution | Organización Europea para la Investigación Nuclear |
language | eng |
publishDate | 2004 |
record_format | invenio |
spelling | cern-8183082019-09-30T06:29:59Zhttp://cds.cern.ch/record/818308engTae Yeon LeeJae Hong ParkDesign and implementation for static Huffman encoding hardware with parallel shifting algorithmDetectors and Experimental TechniquesThis paper presents an implementation of static Huffman encoding hardware for real-time lossless compression in the ECAL of the CMS detector. The construction of the Huffman encoding hardware shows an implementation for optimizing its logic size. The number of logic gates of the parallel shift operation for the hardware is analyzed. Two kinds of implementation methods of the parallel shift operation are compared in aspect of logic size. The experiment with the hardware on a simulated ECAL environment covering 99.9999% of original distribution shows promising result with the simulation that the compression rate was 4.0039 and the maximum length of the stored data in the input buffer was 44. (14 refs).oai:cds.cern.ch:8183082004 |
spellingShingle | Detectors and Experimental Techniques Tae Yeon Lee Jae Hong Park Design and implementation for static Huffman encoding hardware with parallel shifting algorithm |
title | Design and implementation for static Huffman encoding hardware with parallel shifting algorithm |
title_full | Design and implementation for static Huffman encoding hardware with parallel shifting algorithm |
title_fullStr | Design and implementation for static Huffman encoding hardware with parallel shifting algorithm |
title_full_unstemmed | Design and implementation for static Huffman encoding hardware with parallel shifting algorithm |
title_short | Design and implementation for static Huffman encoding hardware with parallel shifting algorithm |
title_sort | design and implementation for static huffman encoding hardware with parallel shifting algorithm |
topic | Detectors and Experimental Techniques |
url | http://cds.cern.ch/record/818308 |
work_keys_str_mv | AT taeyeonlee designandimplementationforstatichuffmanencodinghardwarewithparallelshiftingalgorithm AT jaehongpark designandimplementationforstatichuffmanencodinghardwarewithparallelshiftingalgorithm |