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Design and implementation of static Huffman encoding hardware using a parallel shifting algorithm
This paper discusses the implementation of static Huffman encoding hardware for real-time lossless compression for the electromagnetic calorimeter in the CMS experiment. The construction of the Huffman encoding hardware illustrates the implementation for optimizing the logic size. The number of logi...
Autores principales: | , |
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Lenguaje: | eng |
Publicado: |
2004
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Materias: | |
Acceso en línea: | https://dx.doi.org/10.1109/TNS.2004.834715 http://cds.cern.ch/record/818528 |
_version_ | 1780905486310178816 |
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author | Tae Yeon Lee Jae Hong Park |
author_facet | Tae Yeon Lee Jae Hong Park |
author_sort | Tae Yeon Lee |
collection | CERN |
description | This paper discusses the implementation of static Huffman encoding hardware for real-time lossless compression for the electromagnetic calorimeter in the CMS experiment. The construction of the Huffman encoding hardware illustrates the implementation for optimizing the logic size. The number of logic gates in the parallel shift operation required for the hardware was examined. The experiment with a simulated environment and an FPGA shows that the real-time constraint has been fulfilled and the design of the buffer length is appropriate. (16 refs). |
id | cern-818528 |
institution | Organización Europea para la Investigación Nuclear |
language | eng |
publishDate | 2004 |
record_format | invenio |
spelling | cern-8185282019-09-30T06:29:59Zdoi:10.1109/TNS.2004.834715http://cds.cern.ch/record/818528engTae Yeon LeeJae Hong ParkDesign and implementation of static Huffman encoding hardware using a parallel shifting algorithmDetectors and Experimental TechniquesThis paper discusses the implementation of static Huffman encoding hardware for real-time lossless compression for the electromagnetic calorimeter in the CMS experiment. The construction of the Huffman encoding hardware illustrates the implementation for optimizing the logic size. The number of logic gates in the parallel shift operation required for the hardware was examined. The experiment with a simulated environment and an FPGA shows that the real-time constraint has been fulfilled and the design of the buffer length is appropriate. (16 refs).oai:cds.cern.ch:8185282004 |
spellingShingle | Detectors and Experimental Techniques Tae Yeon Lee Jae Hong Park Design and implementation of static Huffman encoding hardware using a parallel shifting algorithm |
title | Design and implementation of static Huffman encoding hardware using a parallel shifting algorithm |
title_full | Design and implementation of static Huffman encoding hardware using a parallel shifting algorithm |
title_fullStr | Design and implementation of static Huffman encoding hardware using a parallel shifting algorithm |
title_full_unstemmed | Design and implementation of static Huffman encoding hardware using a parallel shifting algorithm |
title_short | Design and implementation of static Huffman encoding hardware using a parallel shifting algorithm |
title_sort | design and implementation of static huffman encoding hardware using a parallel shifting algorithm |
topic | Detectors and Experimental Techniques |
url | https://dx.doi.org/10.1109/TNS.2004.834715 http://cds.cern.ch/record/818528 |
work_keys_str_mv | AT taeyeonlee designandimplementationofstatichuffmanencodinghardwareusingaparallelshiftingalgorithm AT jaehongpark designandimplementationofstatichuffmanencodinghardwareusingaparallelshiftingalgorithm |