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The M.U.5 Computer System
Describes the design of the MU5 research computer, the aim of which has been to produce a high performance machine whose structure is well suited to the needs of modern high level languages. It is hoped that a computing speed improvement of about 20 over the 2-3 mu S instruction rate of ATLAS will b...
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Lenguaje: | eng |
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CERN
1974
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Acceso en línea: | https://dx.doi.org/10.5170/CERN-1974-023.65 http://cds.cern.ch/record/873501 |
_version_ | 1780907681479917568 |
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author | Sumner, F H |
author_facet | Sumner, F H |
author_sort | Sumner, F H |
collection | CERN |
description | Describes the design of the MU5 research computer, the aim of which has been to produce a high performance machine whose structure is well suited to the needs of modern high level languages. It is hoped that a computing speed improvement of about 20 over the 2-3 mu S instruction rate of ATLAS will be obtained. In the ten years which have elapsed between the ATLAS and MU5 projects, the speed of logic gates and main storage has increased by a factor of 8:1, and this will result in a commensurate increase in system performance. In order to approach the 20:1 performance target, however, it will be necessary to adopt extensive parallel processing techniques, and to incorporate data buffering systems to compensate for the disparity between processor and storage speeds. (11 refs). |
id | cern-873501 |
institution | Organización Europea para la Investigación Nuclear |
language | eng |
publishDate | 1974 |
publisher | CERN |
record_format | invenio |
spelling | cern-8735012019-09-30T06:29:59Zdoi:10.5170/CERN-1974-023.65http://cds.cern.ch/record/873501engSumner, F HThe M.U.5 Computer SystemComputing and ComputersDescribes the design of the MU5 research computer, the aim of which has been to produce a high performance machine whose structure is well suited to the needs of modern high level languages. It is hoped that a computing speed improvement of about 20 over the 2-3 mu S instruction rate of ATLAS will be obtained. In the ten years which have elapsed between the ATLAS and MU5 projects, the speed of logic gates and main storage has increased by a factor of 8:1, and this will result in a commensurate increase in system performance. In order to approach the 20:1 performance target, however, it will be necessary to adopt extensive parallel processing techniques, and to incorporate data buffering systems to compensate for the disparity between processor and storage speeds. (11 refs).CERNoai:cds.cern.ch:8735011974 |
spellingShingle | Computing and Computers Sumner, F H The M.U.5 Computer System |
title | The M.U.5 Computer System |
title_full | The M.U.5 Computer System |
title_fullStr | The M.U.5 Computer System |
title_full_unstemmed | The M.U.5 Computer System |
title_short | The M.U.5 Computer System |
title_sort | m.u.5 computer system |
topic | Computing and Computers |
url | https://dx.doi.org/10.5170/CERN-1974-023.65 http://cds.cern.ch/record/873501 |
work_keys_str_mv | AT sumnerfh themu5computersystem AT sumnerfh mu5computersystem |