Cargando…
Cadence® High High-Speed PCB Design Flow: Workshop
Last release of Cadence High-Speed PCB Design methodology (PE142) based on Concept-HDL schematic editor, Constraint Manager, SPECCTRAQuest signal integrity analysis tool and ALLEGRO layout associated with SPECCTRA auto router tools, is now enough developed and stable to be taken into account for hig...
Autor principal: | Sainson, Jean-Michel |
---|---|
Lenguaje: | eng |
Publicado: |
2006
|
Materias: | |
Acceso en línea: | http://cds.cern.ch/record/929928 |
Ejemplares similares
-
Cadence® High-Speed PCB Layout Flow: Workshop
por: Sainson, Jean-Michel
Publicado: (2003) -
Challenges of Implementing A High-Speed PCB Design Flow at CERN: Conference
por: Sainson, Jean-Michel, et al.
Publicado: (2004) -
Méthodologie de Conception de Cartes Rapides: Workshop
por: Sainson, Jean-Michel
Publicado: (2003) -
Printed Circuit Board Signal Integrity Analysis at CERN: POSTER 1/2: Workshop
por: Sainson, Jean-Michel, et al.
Publicado: (2001) -
Printed Circuit Board Signal Integrity Analysis at CERN: POSTER 2/2: Workshop
por: Sainson, Jean-Michel, et al.
Publicado: (2001)