Cadence® High-Speed PCB Layout Flow: Workshop

Last release of Cadence High-Speed PCB Design methodology (PE142) based on Concept-HDL schematic editor, Constraint Manager, SPECCTRAQuest signal integrity analysis tool and ALLEGRO layout associated with SPECCTRA auto router tools, is now enough developed and stable to be taken into account for high-speed board designs at CERN. The implementation of this methodology, build around the new Constraint Manager program, is essential when you have to develop a board having a lot of high-speed design rules such as terminated lines, large bus structures, maximum length, timing, crosstalk etc.. that could not be under control by traditional method. On more conventional designs, formal aspect of the methodology could avoid misunderstanding between hardware and ALLEGRO layout designers, minimizing prototype iteration, development time and price. The capability to keep trace of the original digital designer intents in schematic or board layout, loading formal constraints in EDMS, could also be considered for LHC electronics projects documentation and long term upgrade and maintenance. First part of this training wills overview the methodology with interactive signal integrity analysis capabilities associated with it. A working model, sharing tasks and responsibilities between hardware designers and ALLEGRO layout designers, will be discussed. Second part will presents an evaluation project of the methodology based on a design subset of LHC electronics detector.