An interface solution at 53.76 Gb/s input bandwidth to a single Xilinx Virtex-II Pro FPGA: a practical challenge

When High Energy Physics meets high speed electronics, and state of the art methods fail to deliver the required performance, alternative methods have to be developed. This paper presents a novel solution for hardware trigger processing. Analog signals from 112 inputs are converted into high speed serial data with 12 bit resolution, representing a bandwidth of 53.76 Gb/s of trigger data streamed into a single Xilinx Virtex-II Pro FPGA node. The system automatically corrects for clock phase misalignments of 112 channels, each of those being received at 480 Mb/s. This solution has been implemented in the Trigger Region Unit (TRU) of the ALICE Photon Spectrometer (PHOS) detector, a highly integrated board for processing analogue signals received via intermediate Front-End Electronics cards from a large matrix of PWO crystals.