SystemVerilog for design: a guide to using SystemVerilog for hardware design and modeling

Mostrar otras versiones (1)

Presents the syntax and semantic changes to the SystemVerilog language. Aimed at systems professionals, this book features a chapter that explains the SystemVerilog ""packages"".

Detalles Bibliográficos
Autores principales: Sutherland, Stuart, Davidmann, Simon, Flake, Peter
Lenguaje:eng
Publicado: Springer 2006
Materias:
Computing and Computers
Acceso en línea:http://cds.cern.ch/record/983418
_version_ 1780911146232971264
author Sutherland, Stuart
Davidmann, Simon
Flake, Peter
author_facet Sutherland, Stuart
Davidmann, Simon
Flake, Peter
author_sort Sutherland, Stuart
collection CERN
description Presents the syntax and semantic changes to the SystemVerilog language. Aimed at systems professionals, this book features a chapter that explains the SystemVerilog ""packages"".
id cern-983418
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2006
publisher Springer
record_format invenio
spelling cern-9834182021-04-22T02:10:52Zhttp://cds.cern.ch/record/983418engSutherland, StuartDavidmann, SimonFlake, PeterSystemVerilog for design: a guide to using SystemVerilog for hardware design and modelingComputing and ComputersPresents the syntax and semantic changes to the SystemVerilog language. Aimed at systems professionals, this book features a chapter that explains the SystemVerilog ""packages"".Springeroai:cds.cern.ch:9834182006
spellingShingle Computing and Computers
Sutherland, Stuart
Davidmann, Simon
Flake, Peter
SystemVerilog for design: a guide to using SystemVerilog for hardware design and modeling
title SystemVerilog for design: a guide to using SystemVerilog for hardware design and modeling
title_full SystemVerilog for design: a guide to using SystemVerilog for hardware design and modeling
title_fullStr SystemVerilog for design: a guide to using SystemVerilog for hardware design and modeling
title_full_unstemmed SystemVerilog for design: a guide to using SystemVerilog for hardware design and modeling
title_short SystemVerilog for design: a guide to using SystemVerilog for hardware design and modeling
title_sort systemverilog for design: a guide to using systemverilog for hardware design and modeling
topic Computing and Computers
url http://cds.cern.ch/record/983418
work_keys_str_mv AT sutherlandstuart systemverilogfordesignaguidetousingsystemverilogforhardwaredesignandmodeling
AT davidmannsimon systemverilogfordesignaguidetousingsystemverilogforhardwaredesignandmodeling
AT flakepeter systemverilogfordesignaguidetousingsystemverilogforhardwaredesignandmodeling

Ejemplares similares