Performance evaluation of multiple (32 channels) sub-nanosecond TDC implemented in low-cost FPGA

NA62 experiment Straw tracker frontend board serves as a gas-tight detector cover and integrates two CARIOCA chips, a low cost FPGA (Cyclon III, Altera) and a set of 400Mbit/s links to the backend. The FPGA houses 16 pairs of sub-nanosecond resolution TDCs with derandomizers and an output link seria...

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Detalles Bibliográficos
Autores principales: Lichard, P, Konstantinou, G, Vilanueva, A Villar, Palladino, V
Lenguaje:eng
Publicado: 2014
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.1088/1748-0221/9/03/C03013
http://cds.cern.ch/record/2025659
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author Lichard, P
Konstantinou, G
Vilanueva, A Villar
Palladino, V
author_facet Lichard, P
Konstantinou, G
Vilanueva, A Villar
Palladino, V
author_sort Lichard, P
collection CERN
description NA62 experiment Straw tracker frontend board serves as a gas-tight detector cover and integrates two CARIOCA chips, a low cost FPGA (Cyclon III, Altera) and a set of 400Mbit/s links to the backend. The FPGA houses 16 pairs of sub-nanosecond resolution TDCs with derandomizers and an output link serializer. Evaluation methods, including simulations, and performance results of the system in the lab and on a detector prototype are presented.
id oai-inspirehep.net-1285612
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2014
record_format invenio
spelling oai-inspirehep.net-12856122019-09-30T06:29:59Zdoi:10.1088/1748-0221/9/03/C03013http://cds.cern.ch/record/2025659engLichard, PKonstantinou, GVilanueva, A VillarPalladino, VPerformance evaluation of multiple (32 channels) sub-nanosecond TDC implemented in low-cost FPGADetectors and Experimental TechniquesNA62 experiment Straw tracker frontend board serves as a gas-tight detector cover and integrates two CARIOCA chips, a low cost FPGA (Cyclon III, Altera) and a set of 400Mbit/s links to the backend. The FPGA houses 16 pairs of sub-nanosecond resolution TDCs with derandomizers and an output link serializer. Evaluation methods, including simulations, and performance results of the system in the lab and on a detector prototype are presented.oai:inspirehep.net:12856122014
spellingShingle Detectors and Experimental Techniques
Lichard, P
Konstantinou, G
Vilanueva, A Villar
Palladino, V
Performance evaluation of multiple (32 channels) sub-nanosecond TDC implemented in low-cost FPGA
title Performance evaluation of multiple (32 channels) sub-nanosecond TDC implemented in low-cost FPGA
title_full Performance evaluation of multiple (32 channels) sub-nanosecond TDC implemented in low-cost FPGA
title_fullStr Performance evaluation of multiple (32 channels) sub-nanosecond TDC implemented in low-cost FPGA
title_full_unstemmed Performance evaluation of multiple (32 channels) sub-nanosecond TDC implemented in low-cost FPGA
title_short Performance evaluation of multiple (32 channels) sub-nanosecond TDC implemented in low-cost FPGA
title_sort performance evaluation of multiple (32 channels) sub-nanosecond tdc implemented in low-cost fpga
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.1088/1748-0221/9/03/C03013
http://cds.cern.ch/record/2025659
work_keys_str_mv AT lichardp performanceevaluationofmultiple32channelssubnanosecondtdcimplementedinlowcostfpga
AT konstantinoug performanceevaluationofmultiple32channelssubnanosecondtdcimplementedinlowcostfpga
AT vilanuevaavillar performanceevaluationofmultiple32channelssubnanosecondtdcimplementedinlowcostfpga
AT palladinov performanceevaluationofmultiple32channelssubnanosecondtdcimplementedinlowcostfpga

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