NaNet: a configurable NIC bridging the gap between HPC and real-time HEP GPU computing

NaNet is a FPGA-based PCIe Network Interface Card (NIC) design with GPUDirect and Remote Direct Memory Access (RDMA) capabilities featuring a configurable and extensible set of network channels. The design currently supports both standard—Gbe (1000BASE-T) and 10GbE (10Base-R)—and custom—34 Gbps APEl...

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Detalles Bibliográficos
Autores principales: Lonardo, A, Ameli, F, Ammendola, R, Biagioni, A, Ramusino, A Cotta, Fiorini, M, Frezza, O, Lamanna, G, Lo Cicero, F, Martinelli, M, Neri, I, Paolucci, P S, Pastorelli, E, Pontisso, L, Rossetti, D, Simeone, F, Simula, F, Sozzi, M, Tosoratto, L, Vicini, P
Lenguaje:eng
Publicado: 2015
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.1088/1748-0221/10/04/C04011
http://cds.cern.ch/record/2158983
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author Lonardo, A
Ameli, F
Ammendola, R
Biagioni, A
Ramusino, A Cotta
Fiorini, M
Frezza, O
Lamanna, G
Lo Cicero, F
Martinelli, M
Neri, I
Paolucci, P S
Pastorelli, E
Pontisso, L
Rossetti, D
Simeone, F
Simula, F
Sozzi, M
Tosoratto, L
Vicini, P
author_facet Lonardo, A
Ameli, F
Ammendola, R
Biagioni, A
Ramusino, A Cotta
Fiorini, M
Frezza, O
Lamanna, G
Lo Cicero, F
Martinelli, M
Neri, I
Paolucci, P S
Pastorelli, E
Pontisso, L
Rossetti, D
Simeone, F
Simula, F
Sozzi, M
Tosoratto, L
Vicini, P
author_sort Lonardo, A
collection CERN
description NaNet is a FPGA-based PCIe Network Interface Card (NIC) design with GPUDirect and Remote Direct Memory Access (RDMA) capabilities featuring a configurable and extensible set of network channels. The design currently supports both standard—Gbe (1000BASE-T) and 10GbE (10Base-R)—and custom—34 Gbps APElink and 2.5 Gbps deterministic latency KM3link—channels, but its modularity allows for straightforward inclusion of other link technologies. The GPUDirect feature combined with a transport layer offload module and a data stream processing stage makes NaNet a low-latency NIC suitable for real-time GPU processing. In this paper we describe the NaNet architecture and its performances, exhibiting two of its use cases: the GPU-based low-level trigger for the RICH detector in the NA62 experiment at CERN and the on-/off-shore data transport system for the KM3NeT-IT underwater neutrino telescope.
id oai-inspirehep.net-1359149
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2015
record_format invenio
spelling oai-inspirehep.net-13591492019-09-30T06:29:59Zdoi:10.1088/1748-0221/10/04/C04011http://cds.cern.ch/record/2158983engLonardo, AAmeli, FAmmendola, RBiagioni, ARamusino, A CottaFiorini, MFrezza, OLamanna, GLo Cicero, FMartinelli, MNeri, IPaolucci, P SPastorelli, EPontisso, LRossetti, DSimeone, FSimula, FSozzi, MTosoratto, LVicini, PNaNet: a configurable NIC bridging the gap between HPC and real-time HEP GPU computingDetectors and Experimental TechniquesNaNet is a FPGA-based PCIe Network Interface Card (NIC) design with GPUDirect and Remote Direct Memory Access (RDMA) capabilities featuring a configurable and extensible set of network channels. The design currently supports both standard—Gbe (1000BASE-T) and 10GbE (10Base-R)—and custom—34 Gbps APElink and 2.5 Gbps deterministic latency KM3link—channels, but its modularity allows for straightforward inclusion of other link technologies. The GPUDirect feature combined with a transport layer offload module and a data stream processing stage makes NaNet a low-latency NIC suitable for real-time GPU processing. In this paper we describe the NaNet architecture and its performances, exhibiting two of its use cases: the GPU-based low-level trigger for the RICH detector in the NA62 experiment at CERN and the on-/off-shore data transport system for the KM3NeT-IT underwater neutrino telescope.oai:inspirehep.net:13591492015
spellingShingle Detectors and Experimental Techniques
Lonardo, A
Ameli, F
Ammendola, R
Biagioni, A
Ramusino, A Cotta
Fiorini, M
Frezza, O
Lamanna, G
Lo Cicero, F
Martinelli, M
Neri, I
Paolucci, P S
Pastorelli, E
Pontisso, L
Rossetti, D
Simeone, F
Simula, F
Sozzi, M
Tosoratto, L
Vicini, P
NaNet: a configurable NIC bridging the gap between HPC and real-time HEP GPU computing
title NaNet: a configurable NIC bridging the gap between HPC and real-time HEP GPU computing
title_full NaNet: a configurable NIC bridging the gap between HPC and real-time HEP GPU computing
title_fullStr NaNet: a configurable NIC bridging the gap between HPC and real-time HEP GPU computing
title_full_unstemmed NaNet: a configurable NIC bridging the gap between HPC and real-time HEP GPU computing
title_short NaNet: a configurable NIC bridging the gap between HPC and real-time HEP GPU computing
title_sort nanet: a configurable nic bridging the gap between hpc and real-time hep gpu computing
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.1088/1748-0221/10/04/C04011
http://cds.cern.ch/record/2158983
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