Cargando…
The Phase-I Upgrade of the ATLAS First Level Calorimeter Trigge
The level-1 calorimeter trigger (L1Calo) of the ATLAS experiment has been operating effectively since the start of LHC data taking, and has played a major role in the discovery of the Higgs boson. To face the new challenges posed by the upcoming increases of the LHC proton beam energy and luminosity...
Autor principal: | |
---|---|
Lenguaje: | eng |
Publicado: |
SISSA
2014
|
Materias: | |
Acceso en línea: | https://dx.doi.org/10.22323/1.213.0194 http://cds.cern.ch/record/2025940 |
Sumario: | The level-1 calorimeter trigger (L1Calo) of the ATLAS experiment has been operating effectively since the start of LHC data taking, and has played a major role in the discovery of the Higgs boson. To face the new challenges posed by the upcoming increases of the LHC proton beam energy and luminosity, a series of upgrades is planned for L1Calo. An initial upgrade (Pre-Phase- I) is scheduled to be ready for the start of the second LHC run in 2015, and a further more substantial upgrade (Phase-I) is planned to be installed during the LHC shutdown expected in 2018. The calorimeter trigger aims to identify electrons, photons, taus and hadronic jets. It also determines total and missing transverse energy and can further analyse the event topology using a dedicated system incorporating information from both calorimeter and muon triggers. This paper also presents the Phase-I hardware trigger developments which exploit a tenfold increase in the available calorimeter data granularity when compared to that of the current system. The calorimeter signals will be received via optical fibres and distributed to two distinct processing systems. Those systems implement sliding window algorithms and quasi-offline algorithms to achieve object reconstruction and identification. The algorithms are implemented on high density electronics boards which make use of recent developments in high speed data transmission and FPGA technology. The presentation reviews the physics impact along with the current status of the hardware design, early prototypes and demonstrator boards. |
---|