100 Gbps PCI-Express readout for the LHCb upgrade

We present a new data acquisition system under development for the next upgrade of the LHCb experiment at CERN. We focus in particular on the design of a new generation of readout boards, the PCIe40, and on the viability of PCI-Express as an interconnect technology for high speed readout. We show throughput measurements across the PCI-Express bus, on Altera Stratix 5 devices, using a DMA mechanism and different synchronization schemes between the FPGA and the readout unit. Finally we discuss hardware and software design considerations necessary to achieve a data throughput of 100 Gbps in the final readout board.