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Dynamically Adaptive Header Generator and front-end source emulator for a 100 Gbps FPGA based DAQ
To handle the expected increase in data rate of the LHCb experiment after the upgrade, a new FPGA based DAQ system has been proposed. As a part of this new DAQ system a Dynamically Adaptive Header Generator has been designed and implemented to packetize the streaming data coming, from the Front-end...
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Lenguaje: | eng |
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2014
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Acceso en línea: | https://dx.doi.org/10.1109/RTC.2014.7097510 http://cds.cern.ch/record/2198345 |
_version_ | 1780951250019287040 |
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author | Sridharan, Srikanth |
author_facet | Sridharan, Srikanth |
author_sort | Sridharan, Srikanth |
collection | CERN |
description | To handle the expected increase in data rate of the LHCb experiment after the upgrade, a new FPGA based DAQ system has been proposed. As a part of this new DAQ system a Dynamically Adaptive Header Generator has been designed and implemented to packetize the streaming data coming, from the Front-end electronics of the detectors, for easy access and processing by the Servers. This module also dynamically generates a new data stream by dropping datasets in a controlled fashion in the event of receiving a back pressure signal from the downstream modules. This paper details an architecture that address the need for a DAQ system that effectively balances the 3 conflicting requirements of Real-time operation, Data Integrity and System stability. A synthesizable Front-End Source Emulator has also been implemented to generate data patterns required to test the Header Generator module. This can be used as a test bench for the Header Generator module or a as a standalone module that can be integrated with other systems as required. A system comprising of both the Source Emulator and the header Generator have been implemented on an Altera Stratix IV device and the results discussed. |
id | oai-inspirehep.net-1367439 |
institution | Organización Europea para la Investigación Nuclear |
language | eng |
publishDate | 2014 |
record_format | invenio |
spelling | oai-inspirehep.net-13674392019-09-30T06:29:59Zdoi:10.1109/RTC.2014.7097510http://cds.cern.ch/record/2198345engSridharan, SrikanthDynamically Adaptive Header Generator and front-end source emulator for a 100 Gbps FPGA based DAQDetectors and Experimental TechniquesComputing and ComputersTo handle the expected increase in data rate of the LHCb experiment after the upgrade, a new FPGA based DAQ system has been proposed. As a part of this new DAQ system a Dynamically Adaptive Header Generator has been designed and implemented to packetize the streaming data coming, from the Front-end electronics of the detectors, for easy access and processing by the Servers. This module also dynamically generates a new data stream by dropping datasets in a controlled fashion in the event of receiving a back pressure signal from the downstream modules. This paper details an architecture that address the need for a DAQ system that effectively balances the 3 conflicting requirements of Real-time operation, Data Integrity and System stability. A synthesizable Front-End Source Emulator has also been implemented to generate data patterns required to test the Header Generator module. This can be used as a test bench for the Header Generator module or a as a standalone module that can be integrated with other systems as required. A system comprising of both the Source Emulator and the header Generator have been implemented on an Altera Stratix IV device and the results discussed.oai:inspirehep.net:13674392014 |
spellingShingle | Detectors and Experimental Techniques Computing and Computers Sridharan, Srikanth Dynamically Adaptive Header Generator and front-end source emulator for a 100 Gbps FPGA based DAQ |
title | Dynamically Adaptive Header Generator and front-end source emulator for a 100 Gbps FPGA based DAQ |
title_full | Dynamically Adaptive Header Generator and front-end source emulator for a 100 Gbps FPGA based DAQ |
title_fullStr | Dynamically Adaptive Header Generator and front-end source emulator for a 100 Gbps FPGA based DAQ |
title_full_unstemmed | Dynamically Adaptive Header Generator and front-end source emulator for a 100 Gbps FPGA based DAQ |
title_short | Dynamically Adaptive Header Generator and front-end source emulator for a 100 Gbps FPGA based DAQ |
title_sort | dynamically adaptive header generator and front-end source emulator for a 100 gbps fpga based daq |
topic | Detectors and Experimental Techniques Computing and Computers |
url | https://dx.doi.org/10.1109/RTC.2014.7097510 http://cds.cern.ch/record/2198345 |
work_keys_str_mv | AT sridharansrikanth dynamicallyadaptiveheadergeneratorandfrontendsourceemulatorfora100gbpsfpgabaseddaq |