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Investigation of High-Level Synthesis tools’ applicability to data acquisition systems design based on the CMS ECAL Data Concentrator Card example
High-Level Synthesis (HLS) for Field-Programmable Logic Array (FPGA) programming is becoming a practical alternative to well-established VHDL and Verilog languages. This paper describes a case study in the use of HLS tools to design FPGA-based data acquisition systems (DAQ). We will present the impl...
| Autores principales: | , , |
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| Lenguaje: | eng |
| Publicado: |
2015
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| Materias: | |
| Acceso en línea: | https://dx.doi.org/10.1088/1742-6596/664/8/082019 http://cds.cern.ch/record/2134632 |