A 12 bit 40 MSPS SAR ADC with a redundancy algorithm and digital calibration for the ATLAS LAr calorimeter readout

We present a SAR ADC with a generalized redundant search algorithm offering the flexibility to relax the requirements on the DAC settling time. The redundancy also allows a digital background calibration, based on a code density analysis, to compensate for the capacitor mismatch effects. The total n...

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Detalles Bibliográficos
Autor principal: Zeloufi, M
Lenguaje:eng
Publicado: 2016
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.1088/1748-0221/11/01/C01030
http://cds.cern.ch/record/2266407
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author Zeloufi, M
author_facet Zeloufi, M
author_sort Zeloufi, M
collection CERN
description We present a SAR ADC with a generalized redundant search algorithm offering the flexibility to relax the requirements on the DAC settling time. The redundancy also allows a digital background calibration, based on a code density analysis, to compensate for the capacitor mismatch effects. The total number of capacitors used in this architecture is limited to one half of the one in a classical SAR design. Only 2(11) unit capacitors were necessary to reach 12 bit resolution, and the switching algorithm is intrinsically monotonic. The design is fully differential featuring 12 bit 40 MS/s in a CMOS 130 nm 1P8M process.
id oai-inspirehep.net-1416320
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2016
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spelling oai-inspirehep.net-14163202019-09-30T06:29:59Zdoi:10.1088/1748-0221/11/01/C01030http://cds.cern.ch/record/2266407engZeloufi, MA 12 bit 40 MSPS SAR ADC with a redundancy algorithm and digital calibration for the ATLAS LAr calorimeter readoutDetectors and Experimental TechniquesWe present a SAR ADC with a generalized redundant search algorithm offering the flexibility to relax the requirements on the DAC settling time. The redundancy also allows a digital background calibration, based on a code density analysis, to compensate for the capacitor mismatch effects. The total number of capacitors used in this architecture is limited to one half of the one in a classical SAR design. Only 2(11) unit capacitors were necessary to reach 12 bit resolution, and the switching algorithm is intrinsically monotonic. The design is fully differential featuring 12 bit 40 MS/s in a CMOS 130 nm 1P8M process.oai:inspirehep.net:14163202016
spellingShingle Detectors and Experimental Techniques
Zeloufi, M
A 12 bit 40 MSPS SAR ADC with a redundancy algorithm and digital calibration for the ATLAS LAr calorimeter readout
title A 12 bit 40 MSPS SAR ADC with a redundancy algorithm and digital calibration for the ATLAS LAr calorimeter readout
title_full A 12 bit 40 MSPS SAR ADC with a redundancy algorithm and digital calibration for the ATLAS LAr calorimeter readout
title_fullStr A 12 bit 40 MSPS SAR ADC with a redundancy algorithm and digital calibration for the ATLAS LAr calorimeter readout
title_full_unstemmed A 12 bit 40 MSPS SAR ADC with a redundancy algorithm and digital calibration for the ATLAS LAr calorimeter readout
title_short A 12 bit 40 MSPS SAR ADC with a redundancy algorithm and digital calibration for the ATLAS LAr calorimeter readout
title_sort 12 bit 40 msps sar adc with a redundancy algorithm and digital calibration for the atlas lar calorimeter readout
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.1088/1748-0221/11/01/C01030
http://cds.cern.ch/record/2266407
work_keys_str_mv AT zeloufim a12bit40mspssaradcwitharedundancyalgorithmanddigitalcalibrationfortheatlaslarcalorimeterreadout
AT zeloufim 12bit40mspssaradcwitharedundancyalgorithmanddigitalcalibrationfortheatlaslarcalorimeterreadout

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