A low noise clock generator for high-resolution time-to-digital convertors

A robust PLL clock generator has been designed for the harsh environment in high-energy physics applications. The PLL operates with a reference clock frequency of 40 MHz to 50 MHz and performs a multiplication by 64. An LC tank VCO with low internal phase noise can generate a frequency from 2.2 GHz...

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Detalles Bibliográficos
Autores principales: Prinzie, J, Christiaensen, J, Moreira, P, Steyaert, M, Leroux, P
Lenguaje:eng
Publicado: 2016
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.1088/1748-0221/11/02/C02038
http://cds.cern.ch/record/2139380
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author Prinzie, J
Christiaensen, J
Moreira, P
Steyaert, M
Leroux, P
author_facet Prinzie, J
Christiaensen, J
Moreira, P
Steyaert, M
Leroux, P
author_sort Prinzie, J
collection CERN
description A robust PLL clock generator has been designed for the harsh environment in high-energy physics applications. The PLL operates with a reference clock frequency of 40 MHz to 50 MHz and performs a multiplication by 64. An LC tank VCO with low internal phase noise can generate a frequency from 2.2 GHz up to 3.2 GHz with internal discrete bank switching. The PLL includes an automatic bank selection algorithm to correctly select the correct range of the oscillator. The PLL has been fabricated in a 65 nm CMOS technology and consumes less than 30 mW. The additive jitter of the PLL has been measured to be less than 400 fs RMS.
id oai-inspirehep.net-1421574
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2016
record_format invenio
spelling oai-inspirehep.net-14215742022-08-10T12:45:02Zdoi:10.1088/1748-0221/11/02/C02038http://cds.cern.ch/record/2139380engPrinzie, JChristiaensen, JMoreira, PSteyaert, MLeroux, PA low noise clock generator for high-resolution time-to-digital convertorsDetectors and Experimental TechniquesA robust PLL clock generator has been designed for the harsh environment in high-energy physics applications. The PLL operates with a reference clock frequency of 40 MHz to 50 MHz and performs a multiplication by 64. An LC tank VCO with low internal phase noise can generate a frequency from 2.2 GHz up to 3.2 GHz with internal discrete bank switching. The PLL includes an automatic bank selection algorithm to correctly select the correct range of the oscillator. The PLL has been fabricated in a 65 nm CMOS technology and consumes less than 30 mW. The additive jitter of the PLL has been measured to be less than 400 fs RMS.oai:inspirehep.net:14215742016
spellingShingle Detectors and Experimental Techniques
Prinzie, J
Christiaensen, J
Moreira, P
Steyaert, M
Leroux, P
A low noise clock generator for high-resolution time-to-digital convertors
title A low noise clock generator for high-resolution time-to-digital convertors
title_full A low noise clock generator for high-resolution time-to-digital convertors
title_fullStr A low noise clock generator for high-resolution time-to-digital convertors
title_full_unstemmed A low noise clock generator for high-resolution time-to-digital convertors
title_short A low noise clock generator for high-resolution time-to-digital convertors
title_sort low noise clock generator for high-resolution time-to-digital convertors
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.1088/1748-0221/11/02/C02038
http://cds.cern.ch/record/2139380
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