Ongoing studies for the control system of a serially powered ATLAS pixel detector at the HL-LHC

In terms of the phase-2 upgrade of the ATLAS detector, the entire inner tracker (ITk) of ATLAS will be replaced. This includes the pixel detector and the corresponding detector control system (DCS). The current baseline is a serial powering scheme of the detector modules. Therefore a new detector control system is being developed with emphasis on the supervision of serially powered modules. Previous chips had been designed to test the radiation hardness of the technology and the implementation of the modified I2C as well as the implementation of the logic of the CAN protocol. This included tests with triple redundant registers. The described chip is focusing on the implementation in a serial powering scheme. It was designed for laboratory tests, aiming for the proof of principle. The concept of the DCS for ATLAS pixel after the phase-2 upgrade is presented as well as the status of development including tests with the prototype ASIC.