Cargando…

GBT link testing and performance measurement on PCIe40 and AMC40 custom design FPGA boards

The high-energy physics experiments at the CERN's Large Hadron Collider (LHC) are preparing for Run3, which is foreseen to start in the year 2021. Data from the high radiation environment of the detector front-end electronics are transported to the data processing units, located in low radiatio...

Descripción completa

Detalles Bibliográficos
Autores principales: Mitra, Jubin, Khan, Shuaib A, Marin, Manoel Barros, Cachemiche, Jean-Pierre, David, Erno, Hachon, Fr, Rethore, Fr, Kiss, Tivadar, Baron, Sophie, Kluge, Alex, Nayak, Tapan K
Lenguaje:eng
Publicado: 2016
Materias:
Acceso en línea:https://dx.doi.org/10.1088/1748-0221/11/03/C03039
http://cds.cern.ch/record/2253305
_version_ 1780953638104989696
author Mitra, Jubin
Khan, Shuaib A
Marin, Manoel Barros
Cachemiche, Jean-Pierre
David, Erno
Hachon, Fr
Rethore, Fr
Kiss, Tivadar
Baron, Sophie
Kluge, Alex
Nayak, Tapan K
author_facet Mitra, Jubin
Khan, Shuaib A
Marin, Manoel Barros
Cachemiche, Jean-Pierre
David, Erno
Hachon, Fr
Rethore, Fr
Kiss, Tivadar
Baron, Sophie
Kluge, Alex
Nayak, Tapan K
author_sort Mitra, Jubin
collection CERN
description The high-energy physics experiments at the CERN's Large Hadron Collider (LHC) are preparing for Run3, which is foreseen to start in the year 2021. Data from the high radiation environment of the detector front-end electronics are transported to the data processing units, located in low radiation zones through GBT (Gigabit transceiver) links. The present work discusses the GBT link performance study carried out on custom FPGA boards, clock calibration logic and its implementation in new Arria 10 FPGA.
id oai-inspirehep.net-1430837
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2016
record_format invenio
spelling oai-inspirehep.net-14308372022-08-10T12:39:34Zdoi:10.1088/1748-0221/11/03/C03039http://cds.cern.ch/record/2253305engMitra, JubinKhan, Shuaib AMarin, Manoel BarrosCachemiche, Jean-PierreDavid, ErnoHachon, FrRethore, FrKiss, TivadarBaron, SophieKluge, AlexNayak, Tapan KGBT link testing and performance measurement on PCIe40 and AMC40 custom design FPGA boardsDetectors and Experimental TechniquesThe high-energy physics experiments at the CERN's Large Hadron Collider (LHC) are preparing for Run3, which is foreseen to start in the year 2021. Data from the high radiation environment of the detector front-end electronics are transported to the data processing units, located in low radiation zones through GBT (Gigabit transceiver) links. The present work discusses the GBT link performance study carried out on custom FPGA boards, clock calibration logic and its implementation in new Arria 10 FPGA.oai:inspirehep.net:14308372016
spellingShingle Detectors and Experimental Techniques
Mitra, Jubin
Khan, Shuaib A
Marin, Manoel Barros
Cachemiche, Jean-Pierre
David, Erno
Hachon, Fr
Rethore, Fr
Kiss, Tivadar
Baron, Sophie
Kluge, Alex
Nayak, Tapan K
GBT link testing and performance measurement on PCIe40 and AMC40 custom design FPGA boards
title GBT link testing and performance measurement on PCIe40 and AMC40 custom design FPGA boards
title_full GBT link testing and performance measurement on PCIe40 and AMC40 custom design FPGA boards
title_fullStr GBT link testing and performance measurement on PCIe40 and AMC40 custom design FPGA boards
title_full_unstemmed GBT link testing and performance measurement on PCIe40 and AMC40 custom design FPGA boards
title_short GBT link testing and performance measurement on PCIe40 and AMC40 custom design FPGA boards
title_sort gbt link testing and performance measurement on pcie40 and amc40 custom design fpga boards
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.1088/1748-0221/11/03/C03039
http://cds.cern.ch/record/2253305
work_keys_str_mv AT mitrajubin gbtlinktestingandperformancemeasurementonpcie40andamc40customdesignfpgaboards
AT khanshuaiba gbtlinktestingandperformancemeasurementonpcie40andamc40customdesignfpgaboards
AT marinmanoelbarros gbtlinktestingandperformancemeasurementonpcie40andamc40customdesignfpgaboards
AT cachemichejeanpierre gbtlinktestingandperformancemeasurementonpcie40andamc40customdesignfpgaboards
AT daviderno gbtlinktestingandperformancemeasurementonpcie40andamc40customdesignfpgaboards
AT hachonfr gbtlinktestingandperformancemeasurementonpcie40andamc40customdesignfpgaboards
AT rethorefr gbtlinktestingandperformancemeasurementonpcie40andamc40customdesignfpgaboards
AT kisstivadar gbtlinktestingandperformancemeasurementonpcie40andamc40customdesignfpgaboards
AT baronsophie gbtlinktestingandperformancemeasurementonpcie40andamc40customdesignfpgaboards
AT klugealex gbtlinktestingandperformancemeasurementonpcie40andamc40customdesignfpgaboards
AT nayaktapank gbtlinktestingandperformancemeasurementonpcie40andamc40customdesignfpgaboards