The Phase-Locked Loop Algorithm of the Function Generation/Controller

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This paper describes the phase-locked loop algorithms that are used by the real-time power converter controllers at CERN. The algorithms allow the recovery of the machine time and events received by an embedded controller through WorldFIP or Ethernet-based fieldbuses. During normal operation, the al...

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Detalles Bibliográficos
Autores principales: Magrans de Abril, Marc, King, Quentin, Murillo-Garcia, Raul
Lenguaje:eng
Publicado: 2015
Materias:
Accelerators and Storage Rings
Acceso en línea:https://dx.doi.org/10.18429/JACoW-ICALEPCS2015-WEC3O02
http://cds.cern.ch/record/2213492
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author Magrans de Abril, Marc
King, Quentin
Murillo-Garcia, Raul
author_facet Magrans de Abril, Marc
King, Quentin
Murillo-Garcia, Raul
author_sort Magrans de Abril, Marc
collection CERN
description This paper describes the phase-locked loop algorithms that are used by the real-time power converter controllers at CERN. The algorithms allow the recovery of the machine time and events received by an embedded controller through WorldFIP or Ethernet-based fieldbuses. During normal operation, the algorithm provides less than 10 μs of time precision and 0.5 μs of clock jitter for the WorldFIP case, and less than 2.5 μs of time precision and 40 ns of clock jitter for the Ethernet case.
id oai-inspirehep.net-1481621
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2015
record_format invenio
spelling oai-inspirehep.net-14816212019-09-30T06:29:59Zdoi:10.18429/JACoW-ICALEPCS2015-WEC3O02http://cds.cern.ch/record/2213492engMagrans de Abril, MarcKing, QuentinMurillo-Garcia, RaulThe Phase-Locked Loop Algorithm of the Function Generation/ControllerAccelerators and Storage RingsThis paper describes the phase-locked loop algorithms that are used by the real-time power converter controllers at CERN. The algorithms allow the recovery of the machine time and events received by an embedded controller through WorldFIP or Ethernet-based fieldbuses. During normal operation, the algorithm provides less than 10 μs of time precision and 0.5 μs of clock jitter for the WorldFIP case, and less than 2.5 μs of time precision and 40 ns of clock jitter for the Ethernet case.oai:inspirehep.net:14816212015
spellingShingle Accelerators and Storage Rings
Magrans de Abril, Marc
King, Quentin
Murillo-Garcia, Raul
The Phase-Locked Loop Algorithm of the Function Generation/Controller
title The Phase-Locked Loop Algorithm of the Function Generation/Controller
title_full The Phase-Locked Loop Algorithm of the Function Generation/Controller
title_fullStr The Phase-Locked Loop Algorithm of the Function Generation/Controller
title_full_unstemmed The Phase-Locked Loop Algorithm of the Function Generation/Controller
title_short The Phase-Locked Loop Algorithm of the Function Generation/Controller
title_sort phase-locked loop algorithm of the function generation/controller
topic Accelerators and Storage Rings
url https://dx.doi.org/10.18429/JACoW-ICALEPCS2015-WEC3O02
http://cds.cern.ch/record/2213492
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