A pattern recognition mezzanine based on associative memory and FPGA technology for Level-1 track triggers for the HL-LHC upgrade

Mostrar otras versiones (1)

The increase of luminosity at High Luminosity LHC will require the introduction of tracker information at Level-1 trigger system for the experiments to maintain an acceptable trigger rate to select interesting events despite the one order of magnitude increase in the minimum bias interactions. To ex...

Descripción completa

Detalles Bibliográficos
Autores principales: Bilei, G M, Fedi, G, Magalotti, D, Magazzù, G, Palla, F, Servoli, L
Lenguaje:eng
Publicado: 2016
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.1109/NSSMIC.2015.7581863
http://cds.cern.ch/record/2287313
_version_ 1780956036559011840
author Bilei, G M
Fedi, G
Magalotti, D
Magazzù, G
Palla, F
Servoli, L
author_facet Bilei, G M
Fedi, G
Magalotti, D
Magazzù, G
Palla, F
Servoli, L
author_sort Bilei, G M
collection CERN
description The increase of luminosity at High Luminosity LHC will require the introduction of tracker information at Level-1 trigger system for the experiments to maintain an acceptable trigger rate to select interesting events despite the one order of magnitude increase in the minimum bias interactions. To extract in the required latency the track information a dedicated hardware has to be used. We present the tests of a prototype system (Pattern Recognition Mezzanine) as core of pattern recognition and track fitting for HL-LHC ATLAS and CMS experiments, combining the power of both Associative Memory custom ASIC and modern Field Programmable Gate Array (FPGA) devices.
id oai-inspirehep.net-1498874
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2016
record_format invenio
spelling oai-inspirehep.net-14988742022-08-17T12:59:34Zdoi:10.1109/NSSMIC.2015.7581863http://cds.cern.ch/record/2287313engBilei, G MFedi, GMagalotti, DMagazzù, GPalla, FServoli, LA pattern recognition mezzanine based on associative memory and FPGA technology for Level-1 track triggers for the HL-LHC upgradeDetectors and Experimental TechniquesThe increase of luminosity at High Luminosity LHC will require the introduction of tracker information at Level-1 trigger system for the experiments to maintain an acceptable trigger rate to select interesting events despite the one order of magnitude increase in the minimum bias interactions. To extract in the required latency the track information a dedicated hardware has to be used. We present the tests of a prototype system (Pattern Recognition Mezzanine) as core of pattern recognition and track fitting for HL-LHC ATLAS and CMS experiments, combining the power of both Associative Memory custom ASIC and modern Field Programmable Gate Array (FPGA) devices.oai:inspirehep.net:14988742016
spellingShingle Detectors and Experimental Techniques
Bilei, G M
Fedi, G
Magalotti, D
Magazzù, G
Palla, F
Servoli, L
A pattern recognition mezzanine based on associative memory and FPGA technology for Level-1 track triggers for the HL-LHC upgrade
title A pattern recognition mezzanine based on associative memory and FPGA technology for Level-1 track triggers for the HL-LHC upgrade
title_full A pattern recognition mezzanine based on associative memory and FPGA technology for Level-1 track triggers for the HL-LHC upgrade
title_fullStr A pattern recognition mezzanine based on associative memory and FPGA technology for Level-1 track triggers for the HL-LHC upgrade
title_full_unstemmed A pattern recognition mezzanine based on associative memory and FPGA technology for Level-1 track triggers for the HL-LHC upgrade
title_short A pattern recognition mezzanine based on associative memory and FPGA technology for Level-1 track triggers for the HL-LHC upgrade
title_sort pattern recognition mezzanine based on associative memory and fpga technology for level-1 track triggers for the hl-lhc upgrade
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.1109/NSSMIC.2015.7581863
http://cds.cern.ch/record/2287313
work_keys_str_mv AT bileigm apatternrecognitionmezzaninebasedonassociativememoryandfpgatechnologyforlevel1tracktriggersforthehllhcupgrade
AT fedig apatternrecognitionmezzaninebasedonassociativememoryandfpgatechnologyforlevel1tracktriggersforthehllhcupgrade
AT magalottid apatternrecognitionmezzaninebasedonassociativememoryandfpgatechnologyforlevel1tracktriggersforthehllhcupgrade
AT magazzug apatternrecognitionmezzaninebasedonassociativememoryandfpgatechnologyforlevel1tracktriggersforthehllhcupgrade
AT pallaf apatternrecognitionmezzaninebasedonassociativememoryandfpgatechnologyforlevel1tracktriggersforthehllhcupgrade
AT servolil apatternrecognitionmezzaninebasedonassociativememoryandfpgatechnologyforlevel1tracktriggersforthehllhcupgrade
AT bileigm patternrecognitionmezzaninebasedonassociativememoryandfpgatechnologyforlevel1tracktriggersforthehllhcupgrade
AT fedig patternrecognitionmezzaninebasedonassociativememoryandfpgatechnologyforlevel1tracktriggersforthehllhcupgrade
AT magalottid patternrecognitionmezzaninebasedonassociativememoryandfpgatechnologyforlevel1tracktriggersforthehllhcupgrade
AT magazzug patternrecognitionmezzaninebasedonassociativememoryandfpgatechnologyforlevel1tracktriggersforthehllhcupgrade
AT pallaf patternrecognitionmezzaninebasedonassociativememoryandfpgatechnologyforlevel1tracktriggersforthehllhcupgrade
AT servolil patternrecognitionmezzaninebasedonassociativememoryandfpgatechnologyforlevel1tracktriggersforthehllhcupgrade

Ejemplares similares