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The VeloPix ASIC

VeloPix, a 130 nm CMOS technology chip with data driven and zero suppressed readout, will be used as a readout chip for the hybrid pixel system of the LHCb Vertex Locator (VELO) upgrade. The upgrade, scheduled for LHC Run-3, will enable the experiment to be read out at 40 MHz in trigger-less mode, w...

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Detalles Bibliográficos
Autores principales:	Poikela, Tuomas, Ballabriga, R, Buytaert, J, Llopart, X, Wong, W, Campbell, M, Wyllie, K, van Beuzekom, M, Schipper, J, Miryala, S, Gromov, V
Lenguaje:	eng
Publicado:	2017
Materias:	Detectors and Experimental Techniques
Acceso en línea:	https://dx.doi.org/10.1088/1748-0221/12/01/C01070 http://cds.cern.ch/record/2275005

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