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A 65 nm CMOS analog processor with zero dead time for future pixel detectors

Next generation pixel chips at the High-Luminosity (HL) LHC will be exposed to extremely high levels of radiation and particle rates. In the so-called Phase II upgrade, ATLAS and CMS will need a completely new tracker detector, complying with the very demanding operating conditions and the delivered...

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Detalles Bibliográficos
Autores principales: Gaioni, L, Braga, D, Christian, D C, Deptuch, G, Fahim, F, Nodari, B, Ratti, L, Re, V, Zimmerman, T
Lenguaje:eng
Publicado: 2017
Materias:
Acceso en línea:https://dx.doi.org/10.1016/j.nima.2016.04.053
http://cds.cern.ch/record/2291592
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author Gaioni, L
Braga, D
Christian, D C
Deptuch, G
Fahim, F
Nodari, B
Ratti, L
Re, V
Zimmerman, T
author_facet Gaioni, L
Braga, D
Christian, D C
Deptuch, G
Fahim, F
Nodari, B
Ratti, L
Re, V
Zimmerman, T
author_sort Gaioni, L
collection CERN
description Next generation pixel chips at the High-Luminosity (HL) LHC will be exposed to extremely high levels of radiation and particle rates. In the so-called Phase II upgrade, ATLAS and CMS will need a completely new tracker detector, complying with the very demanding operating conditions and the delivered luminosity (up to 5×10 34 cm −2 s −1 in the next decade). This work is concerned with the design of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier featuring a detector leakage compensation circuit, and a compact, single ended comparator that guarantees very good performance in terms of channel-to-channel dispersion of threshold without needing any pixel-level trimming. A flash ADC is exploited for digital conversion immediately after the charge amplifier. A thorough discussion on the design of the charge amplifier and the comparator is provided along with an exhaustive set of simulation results.
id oai-inspirehep.net-1513605
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2017
record_format invenio
spelling oai-inspirehep.net-15136052019-09-30T06:29:59Zdoi:10.1016/j.nima.2016.04.053http://cds.cern.ch/record/2291592engGaioni, LBraga, DChristian, D CDeptuch, GFahim, FNodari, BRatti, LRe, VZimmerman, TA 65 nm CMOS analog processor with zero dead time for future pixel detectorsDetectors and Experimental TechniquesNext generation pixel chips at the High-Luminosity (HL) LHC will be exposed to extremely high levels of radiation and particle rates. In the so-called Phase II upgrade, ATLAS and CMS will need a completely new tracker detector, complying with the very demanding operating conditions and the delivered luminosity (up to 5×10 34 cm −2 s −1 in the next decade). This work is concerned with the design of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier featuring a detector leakage compensation circuit, and a compact, single ended comparator that guarantees very good performance in terms of channel-to-channel dispersion of threshold without needing any pixel-level trimming. A flash ADC is exploited for digital conversion immediately after the charge amplifier. A thorough discussion on the design of the charge amplifier and the comparator is provided along with an exhaustive set of simulation results.oai:inspirehep.net:15136052017
spellingShingle Detectors and Experimental Techniques
Gaioni, L
Braga, D
Christian, D C
Deptuch, G
Fahim, F
Nodari, B
Ratti, L
Re, V
Zimmerman, T
A 65 nm CMOS analog processor with zero dead time for future pixel detectors
title A 65 nm CMOS analog processor with zero dead time for future pixel detectors
title_full A 65 nm CMOS analog processor with zero dead time for future pixel detectors
title_fullStr A 65 nm CMOS analog processor with zero dead time for future pixel detectors
title_full_unstemmed A 65 nm CMOS analog processor with zero dead time for future pixel detectors
title_short A 65 nm CMOS analog processor with zero dead time for future pixel detectors
title_sort 65 nm cmos analog processor with zero dead time for future pixel detectors
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.1016/j.nima.2016.04.053
http://cds.cern.ch/record/2291592
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