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Graphical processors for HEP trigger systems

General-purpose computing on GPUs is emerging as a new paradigm in several fields of science, although so far applications have been tailored to employ GPUs as accelerators in offline computations. With the steady decrease of GPU latencies and the increase in link and memory throughputs, time is rip...

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Detalles Bibliográficos
Autores principales: Ammendola, R, Biagioni, A, Chiozzi, S, Cotta Ramusino, A, Di Lorenzo, S, Fantechi, R, Fiorini, M, Frezza, O, Lamanna, G, Lo Cicero, F, Lonardo, A, Martinelli, M, Neri, I, Paolucci, P S, Pastorelli, E, Piandani, R, Pontisso, L, Rossetti, D, Simula, F, Sozzi, M, Vicini, P
Lenguaje:eng
Publicado: 2017
Materias:
Acceso en línea:https://dx.doi.org/10.1016/j.nima.2016.06.043
http://cds.cern.ch/record/2291595
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author Ammendola, R
Biagioni, A
Chiozzi, S
Cotta Ramusino, A
Di Lorenzo, S
Fantechi, R
Fiorini, M
Frezza, O
Lamanna, G
Lo Cicero, F
Lonardo, A
Martinelli, M
Neri, I
Paolucci, P S
Pastorelli, E
Piandani, R
Pontisso, L
Rossetti, D
Simula, F
Sozzi, M
Vicini, P
author_facet Ammendola, R
Biagioni, A
Chiozzi, S
Cotta Ramusino, A
Di Lorenzo, S
Fantechi, R
Fiorini, M
Frezza, O
Lamanna, G
Lo Cicero, F
Lonardo, A
Martinelli, M
Neri, I
Paolucci, P S
Pastorelli, E
Piandani, R
Pontisso, L
Rossetti, D
Simula, F
Sozzi, M
Vicini, P
author_sort Ammendola, R
collection CERN
description General-purpose computing on GPUs is emerging as a new paradigm in several fields of science, although so far applications have been tailored to employ GPUs as accelerators in offline computations. With the steady decrease of GPU latencies and the increase in link and memory throughputs, time is ripe for real-time applications using GPUs in high-energy physics data acquisition and trigger systems. We will discuss the use of online parallel computing on GPUs for synchronous low level trigger systems, focusing on tests performed on the trigger of the CERN NA62 experiment. Latencies of all components need analysing, networking being the most critical. To keep it under control, we envisioned NaNet, an FPGA-based PCIe Network Interface Card (NIC) enabling GPUDirect connection. Moreover, we discuss how specific trigger algorithms can be parallelised and thus benefit from a GPU implementation, in terms of increased execution speed. Such improvements are particularly relevant for the foreseen LHC luminosity upgrade where highly selective algorithms will be crucial to maintain sustainable trigger rates with very high pileup.
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institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2017
record_format invenio
spelling oai-inspirehep.net-15136192019-09-30T06:29:59Zdoi:10.1016/j.nima.2016.06.043http://cds.cern.ch/record/2291595engAmmendola, RBiagioni, AChiozzi, SCotta Ramusino, ADi Lorenzo, SFantechi, RFiorini, MFrezza, OLamanna, GLo Cicero, FLonardo, AMartinelli, MNeri, IPaolucci, P SPastorelli, EPiandani, RPontisso, LRossetti, DSimula, FSozzi, MVicini, PGraphical processors for HEP trigger systemsDetectors and Experimental TechniquesComputing and ComputersGeneral-purpose computing on GPUs is emerging as a new paradigm in several fields of science, although so far applications have been tailored to employ GPUs as accelerators in offline computations. With the steady decrease of GPU latencies and the increase in link and memory throughputs, time is ripe for real-time applications using GPUs in high-energy physics data acquisition and trigger systems. We will discuss the use of online parallel computing on GPUs for synchronous low level trigger systems, focusing on tests performed on the trigger of the CERN NA62 experiment. Latencies of all components need analysing, networking being the most critical. To keep it under control, we envisioned NaNet, an FPGA-based PCIe Network Interface Card (NIC) enabling GPUDirect connection. Moreover, we discuss how specific trigger algorithms can be parallelised and thus benefit from a GPU implementation, in terms of increased execution speed. Such improvements are particularly relevant for the foreseen LHC luminosity upgrade where highly selective algorithms will be crucial to maintain sustainable trigger rates with very high pileup.oai:inspirehep.net:15136192017
spellingShingle Detectors and Experimental Techniques
Computing and Computers
Ammendola, R
Biagioni, A
Chiozzi, S
Cotta Ramusino, A
Di Lorenzo, S
Fantechi, R
Fiorini, M
Frezza, O
Lamanna, G
Lo Cicero, F
Lonardo, A
Martinelli, M
Neri, I
Paolucci, P S
Pastorelli, E
Piandani, R
Pontisso, L
Rossetti, D
Simula, F
Sozzi, M
Vicini, P
Graphical processors for HEP trigger systems
title Graphical processors for HEP trigger systems
title_full Graphical processors for HEP trigger systems
title_fullStr Graphical processors for HEP trigger systems
title_full_unstemmed Graphical processors for HEP trigger systems
title_short Graphical processors for HEP trigger systems
title_sort graphical processors for hep trigger systems
topic Detectors and Experimental Techniques
Computing and Computers
url https://dx.doi.org/10.1016/j.nima.2016.06.043
http://cds.cern.ch/record/2291595
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