Advanced power analysis methodology targeted to the optimization of a digital pixel readout chip design and its critical serial powering system

A dedicated power analysis methodology, based on modern digital design tools and integrated with the VEPIX53 simulation framework developed within RD53 collaboration, is being used to guide vital choices for the design and optimization of the next generation ATLAS and CMS pixel chips and their criti...

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Detalles Bibliográficos
Autores principales: Marconi, S, Orfanelli, S, Karagounis, M, Hemperek, T, Christiansen, J, Placidi, P
Lenguaje:eng
Publicado: 2017
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.1088/1748-0221/12/02/C02017
http://cds.cern.ch/record/2275132
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author Marconi, S
Orfanelli, S
Karagounis, M
Hemperek, T
Christiansen, J
Placidi, P
author_facet Marconi, S
Orfanelli, S
Karagounis, M
Hemperek, T
Christiansen, J
Placidi, P
author_sort Marconi, S
collection CERN
description A dedicated power analysis methodology, based on modern digital design tools and integrated with the VEPIX53 simulation framework developed within RD53 collaboration, is being used to guide vital choices for the design and optimization of the next generation ATLAS and CMS pixel chips and their critical serial powering circuit (shunt-LDO). Power consumption is studied at different stages of the design flow under different operating conditions. Significant effort is put into extensive investigations of dynamic power variations in relation with the decoupling seen by the powering network. Shunt-LDO simulations are also reported to prove the reliability at the system level.
id oai-inspirehep.net-1513696
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2017
record_format invenio
spelling oai-inspirehep.net-15136962019-10-15T15:19:45Zdoi:10.1088/1748-0221/12/02/C02017http://cds.cern.ch/record/2275132engMarconi, SOrfanelli, SKaragounis, MHemperek, TChristiansen, JPlacidi, PAdvanced power analysis methodology targeted to the optimization of a digital pixel readout chip design and its critical serial powering systemDetectors and Experimental TechniquesA dedicated power analysis methodology, based on modern digital design tools and integrated with the VEPIX53 simulation framework developed within RD53 collaboration, is being used to guide vital choices for the design and optimization of the next generation ATLAS and CMS pixel chips and their critical serial powering circuit (shunt-LDO). Power consumption is studied at different stages of the design flow under different operating conditions. Significant effort is put into extensive investigations of dynamic power variations in relation with the decoupling seen by the powering network. Shunt-LDO simulations are also reported to prove the reliability at the system level.oai:inspirehep.net:15136962017
spellingShingle Detectors and Experimental Techniques
Marconi, S
Orfanelli, S
Karagounis, M
Hemperek, T
Christiansen, J
Placidi, P
Advanced power analysis methodology targeted to the optimization of a digital pixel readout chip design and its critical serial powering system
title Advanced power analysis methodology targeted to the optimization of a digital pixel readout chip design and its critical serial powering system
title_full Advanced power analysis methodology targeted to the optimization of a digital pixel readout chip design and its critical serial powering system
title_fullStr Advanced power analysis methodology targeted to the optimization of a digital pixel readout chip design and its critical serial powering system
title_full_unstemmed Advanced power analysis methodology targeted to the optimization of a digital pixel readout chip design and its critical serial powering system
title_short Advanced power analysis methodology targeted to the optimization of a digital pixel readout chip design and its critical serial powering system
title_sort advanced power analysis methodology targeted to the optimization of a digital pixel readout chip design and its critical serial powering system
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.1088/1748-0221/12/02/C02017
http://cds.cern.ch/record/2275132
work_keys_str_mv AT marconis advancedpoweranalysismethodologytargetedtotheoptimizationofadigitalpixelreadoutchipdesignanditscriticalserialpoweringsystem
AT orfanellis advancedpoweranalysismethodologytargetedtotheoptimizationofadigitalpixelreadoutchipdesignanditscriticalserialpoweringsystem
AT karagounism advancedpoweranalysismethodologytargetedtotheoptimizationofadigitalpixelreadoutchipdesignanditscriticalserialpoweringsystem
AT hemperekt advancedpoweranalysismethodologytargetedtotheoptimizationofadigitalpixelreadoutchipdesignanditscriticalserialpoweringsystem
AT christiansenj advancedpoweranalysismethodologytargetedtotheoptimizationofadigitalpixelreadoutchipdesignanditscriticalserialpoweringsystem
AT placidip advancedpoweranalysismethodologytargetedtotheoptimizationofadigitalpixelreadoutchipdesignanditscriticalserialpoweringsystem

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