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SAMPA Chip: the New 32 Channels ASIC for the ALICE TPC and MCH Upgrades

This paper presents the test results of the second prototype of SAMPA, the ASIC designed for the upgrade of read-out front end electronics of the ALICE Time Projection Chamber (TPC) and Muon Chamber (MCH). SAMPA is made in a 130 nm CMOS technology with 1.25 V nominal voltage supply and provides 32 c...

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Autores principales: Adolfsson, J, Pabon, A Ayala, Bregant, M, Britton, C, Brulin, G, Carvalho, D, Chambert, V, Chinellato, D, Espagnon, B, Herrera, H D Hernandez, Ljubicic, T, Mahmood, S M, Mjörnmark, U, Moraes, D, Munhoz, M G, Noël, G, Oskarsson, A, Osterman, L, Pilyar, A, Read, K, Ruette, A, Russo, P, Sanches, B C S, Severo, L, Silvermyr, D, Suire, C, Tambave, G J, Tun-Lanoë, K M M, Noije, W van, Velure, A, Vereschagin, S, Wanlin, E, Weber, T O, Zaporozhets, S
Lenguaje:eng
Publicado: 2017
Materias:
Acceso en línea:https://dx.doi.org/10.1088/1748-0221/12/04/C04008
http://cds.cern.ch/record/2291600
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author Adolfsson, J
Pabon, A Ayala
Bregant, M
Britton, C
Brulin, G
Carvalho, D
Chambert, V
Chinellato, D
Espagnon, B
Herrera, H D Hernandez
Ljubicic, T
Mahmood, S M
Mjörnmark, U
Moraes, D
Munhoz, M G
Noël, G
Oskarsson, A
Osterman, L
Pilyar, A
Read, K
Ruette, A
Russo, P
Sanches, B C S
Severo, L
Silvermyr, D
Suire, C
Tambave, G J
Tun-Lanoë, K M M
Noije, W van
Velure, A
Vereschagin, S
Wanlin, E
Weber, T O
Zaporozhets, S
author_facet Adolfsson, J
Pabon, A Ayala
Bregant, M
Britton, C
Brulin, G
Carvalho, D
Chambert, V
Chinellato, D
Espagnon, B
Herrera, H D Hernandez
Ljubicic, T
Mahmood, S M
Mjörnmark, U
Moraes, D
Munhoz, M G
Noël, G
Oskarsson, A
Osterman, L
Pilyar, A
Read, K
Ruette, A
Russo, P
Sanches, B C S
Severo, L
Silvermyr, D
Suire, C
Tambave, G J
Tun-Lanoë, K M M
Noije, W van
Velure, A
Vereschagin, S
Wanlin, E
Weber, T O
Zaporozhets, S
author_sort Adolfsson, J
collection CERN
description This paper presents the test results of the second prototype of SAMPA, the ASIC designed for the upgrade of read-out front end electronics of the ALICE Time Projection Chamber (TPC) and Muon Chamber (MCH). SAMPA is made in a 130 nm CMOS technology with 1.25 V nominal voltage supply and provides 32 channels, with selectable input polarity, and three possible combinations of shaping time and sensitivity. Each channel consists of a Charge Sensitive Amplifier, a semi-Gaussian shaper and a 10-bit ADC, a Digital Signal Processor provides digital filtering and compression capability. In the second prototype run both full chip and single test blocks were fabricated, allowing block characterization and full system behaviour studies. Experimental results are here presented showing agreement with requirements for both the blocks and the full chip.
id oai-inspirehep.net-1591414
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2017
record_format invenio
spelling oai-inspirehep.net-15914142019-09-30T06:29:59Zdoi:10.1088/1748-0221/12/04/C04008http://cds.cern.ch/record/2291600engAdolfsson, JPabon, A AyalaBregant, MBritton, CBrulin, GCarvalho, DChambert, VChinellato, DEspagnon, BHerrera, H D HernandezLjubicic, TMahmood, S MMjörnmark, UMoraes, DMunhoz, M GNoël, GOskarsson, AOsterman, LPilyar, ARead, KRuette, ARusso, PSanches, B C SSevero, LSilvermyr, DSuire, CTambave, G JTun-Lanoë, K M MNoije, W vanVelure, AVereschagin, SWanlin, EWeber, T OZaporozhets, SSAMPA Chip: the New 32 Channels ASIC for the ALICE TPC and MCH UpgradesDetectors and Experimental TechniquesThis paper presents the test results of the second prototype of SAMPA, the ASIC designed for the upgrade of read-out front end electronics of the ALICE Time Projection Chamber (TPC) and Muon Chamber (MCH). SAMPA is made in a 130 nm CMOS technology with 1.25 V nominal voltage supply and provides 32 channels, with selectable input polarity, and three possible combinations of shaping time and sensitivity. Each channel consists of a Charge Sensitive Amplifier, a semi-Gaussian shaper and a 10-bit ADC, a Digital Signal Processor provides digital filtering and compression capability. In the second prototype run both full chip and single test blocks were fabricated, allowing block characterization and full system behaviour studies. Experimental results are here presented showing agreement with requirements for both the blocks and the full chip.oai:inspirehep.net:15914142017
spellingShingle Detectors and Experimental Techniques
Adolfsson, J
Pabon, A Ayala
Bregant, M
Britton, C
Brulin, G
Carvalho, D
Chambert, V
Chinellato, D
Espagnon, B
Herrera, H D Hernandez
Ljubicic, T
Mahmood, S M
Mjörnmark, U
Moraes, D
Munhoz, M G
Noël, G
Oskarsson, A
Osterman, L
Pilyar, A
Read, K
Ruette, A
Russo, P
Sanches, B C S
Severo, L
Silvermyr, D
Suire, C
Tambave, G J
Tun-Lanoë, K M M
Noije, W van
Velure, A
Vereschagin, S
Wanlin, E
Weber, T O
Zaporozhets, S
SAMPA Chip: the New 32 Channels ASIC for the ALICE TPC and MCH Upgrades
title SAMPA Chip: the New 32 Channels ASIC for the ALICE TPC and MCH Upgrades
title_full SAMPA Chip: the New 32 Channels ASIC for the ALICE TPC and MCH Upgrades
title_fullStr SAMPA Chip: the New 32 Channels ASIC for the ALICE TPC and MCH Upgrades
title_full_unstemmed SAMPA Chip: the New 32 Channels ASIC for the ALICE TPC and MCH Upgrades
title_short SAMPA Chip: the New 32 Channels ASIC for the ALICE TPC and MCH Upgrades
title_sort sampa chip: the new 32 channels asic for the alice tpc and mch upgrades
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.1088/1748-0221/12/04/C04008
http://cds.cern.ch/record/2291600
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