Proof of principle of an on-line digitizer with ±18 ppm repeatability and 1.2 μs real-time delay for power converters control loop

The proof of principle of an on-line digitizer designed to be integrated into the digital control loop of a high-voltage modulator for ultra-repeatable power converters is presented. The presented selective analogue zoom allows digitizing with ± 18 ppm repeatability the voltage around the nominal level (10 V± 1 V) and, at the same time, the initial transients with relaxed performance. In addition, in order not to jeopardize the digital control loop stability, the whole digitizing system has to introduce a low real-time delay, this is assessed to be less than 1.2 μs. Initially, the specifications of the real-time control are presented and translated into data acquisition requirements. Then, the main design choices of the digitizer are discussed and Pspice simulation results are reported to validate the concept design. Finally, experimental results of a validation case study developed for the power converter designed at ETH Zurich and University of Laval for the new linear particle accelerator under study at CERN, the Compact LInear Collider CLIC, are reported and compared with the simulation outcomes.