Exploring FPGA hardening solutions at the detector level for the future high luminosity phase of the CMS experiment at the LHC

The objective of the GE1/1 project which is under development since 2010, is to install tripleGEM detectors in the endcaps area of Compact Muons Solenoid (CMS) experiment, one of the four main experiments of the Large Hadron Collider (LHC). This master thesis is a contribution to the development of the Data Acquisition electronics (DAQ) of the project, more precisely on the necessity of the radiation hardening of the FPGA on the Opto-Hybrid board (OH). First of all, an overview of the interactions between incident particles and electronic devices and the categorisation of the different possible induced misbehaviours is given. Moreover, the simulations on the environment inside CMS are presented and are followed by a description of different existing mitigation techniques for electronic devices found in the literature. The second part of this thesis is about the development of a firmware in order to test the different resources (CLB, BRAM and configuration memory) of the FPGA with and without mitigation techniques. In order to test the CLB, the Triple Modular Redundancy (TMR) mitigation technique was chosen and applied to the zero suppression module. The latter is a critical part of the firmware which will be implemented on the FPGA at the end. Concerning the BRAM, the IP ”block memory generator” has a feature called Error Correction Capability (ECC) that allows to detect and correct upsets by the use of Hamming code. Finally, the configuration memory use the Soft Error Mitigation (SEM) IP in order to detect and correct upset in it. The firmware was tested at the UCL cyclotron Cyclone. The FPGA was irradiated by a beam of protons with a flux several order higher than those predicted inside CMS. This allowed to observe a significant amount of upsets in it but also to reach a Total Ionizing Dose (TID) of 84 krad comparing to the 10 krad predicted by simulations as the accumulated dose at the end of operations of the LHC. The analysis revealed the FPGA is still working well after a TID of 84 krad. The FPGA is then adapted to working properly until the end of operations of the LHC. The ECC for the BRAM was able to correct every single upsets and detect double upsets. Concerning SEM, upsets in configuration memory were detected and around 90 % were corrected within a few milliseconds. This reveals the necessity of the mitigation of logic implemented on the FPGA. Unfortunately, TMR could not be tested due to a malfunction of the firmware. Thus, more tests will be necessary in order to determine the efficiency of this mitigation technique.