Implementation of an FPGA based calibration procedure at the detector level for the future high-luminosity phase of the CMS

The GE1/1 project, which started in 2010, has for objective to install triple-GEM detectors -along with their acquisition chain- in the Compact Muons Solenoid (CMS), one of the 4 experiments of the Large Hadron Collider (LHC). This master thesis is a contribution to the development and the commissioning of the acquisition electronics (DAQ) of the project, and more precisely of the VFATs, the first chips in this chain. After the description of the LHC and CMS, the GE1/1 project and its acquisition electronics, this master thesis presents the implementation of a calibration procedure for the VFATs. To do so, the thesis starts by developing firmwares and software routines which, in an automated way, scan the VFATs, collect a maximum of information and set the registers depending on the results, in order to ensure an optimized functioning of the chips during their operations. Since the GE1/1 project is still under development, the second part of the master thesis presents a series of studies performed with the calibration procedure on existing prototypes of the detector and its acquisition electronics. These systematic studies have allowed to observe several issues related to unexpected noise, and helped to solve most of them. Finally, the master thesis discusses the VFAT noise when the chip is connected and not connected to the CMS triple-GEM detector, and compares the measurement with the theoretical prediction. This study highlights the dependence of the noise on the detector capacitance.