Performance evaluation of digital pixel readout chip architecture operating at very high rate through a reusable UVM simulation framework

A large scale demonstrator pixel readout chip is currently being designed by the RD53 Collaboration, with the goal of proving the suitability of 65 nm technology for the extreme operating conditions associated to the High Luminosity upgrades of the ATLAS and CMS experiments at the Large Hadron Collider. The VEPIX53 simulation and verification environment was developed in order to support the chip design flow at different steps, from architectural modeling and optimization to final design verification, thanks to the flexibility and reusability of System Verilog and the Universal Verification Methodology (UVM) library. In this work a test case of VEPIX53 is presented where an existing digital pixel architecture, already implemented in a small scale prototype chip, is simulated for evaluating whether it satisfies the specifications of the large scale demonstrator chip. The architecture inefficiency was measured by the analysis components of the environment, with respect to different models of analog front-ends and different pixel hit memory sizes, showing possible solutions for optimization.