Cargando…
Performance evaluation of digital pixel readout chip architecture operating at very high rate through a reusable UVM simulation framework
A large scale demonstrator pixel readout chip is currently being designed by the RD53 Collaboration, with the goal of proving the suitability of 65 nm technology for the extreme operating conditions associated to the High Luminosity upgrades of the ATLAS and CMS experiments at the Large Hadron Colli...
| Autores principales: | , , , , |
|---|---|
| Lenguaje: | eng |
| Publicado: |
2017
|
| Materias: | |
| Acceso en línea: | https://dx.doi.org/10.1109/NSSMIC.2016.8069646 http://cds.cern.ch/record/2623947 |