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Low-power optimisation of a pixel array architecture for next generation High Energy Physics detectors
A large scale pixel readout chip is being designed by the RD53 Collaboration, in order to prove the suitability of 65 nm technology for the extreme operating conditions foreseen for the High Luminosity upgrades of the ATLAS and CMS experiments at CERN. The use of advanced digital design and simulati...
| Autores principales: | , , , , , |
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| Lenguaje: | eng |
| Publicado: |
2017
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| Materias: | |
| Acceso en línea: | https://dx.doi.org/10.1109/PRIME.2017.7974142 http://cds.cern.ch/record/2314731 |