Experimental Methods and Results for the Evaluation of Triple Modular Redundancy SEU Mitigation Techniques with the Xilinx Kintex-7 FPGA

This paper describes experimental methods and results for the evaluation of triple modular redundancy SEU mitigation techniques with the Xilinx Kintex-7 FPGA. Testing was performed both in proton irradiation and fault injection tests.

Detalles Bibliográficos
Autores principales: Sielewicz, Krzysztof M, Rinella, Gianluca Aglieri, Bonora, Matthias, Giubilato, Piero, Lupi, Matteo, Rossewij, Marcus J, Schambach, Joachim, Vanat, Tomas
Lenguaje:eng
Publicado: 2017
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.1109/NSREC.2017.8115451
http://cds.cern.ch/record/2303669
Descripción
Sumario:This paper describes experimental methods and results for the evaluation of triple modular redundancy SEU mitigation techniques with the Xilinx Kintex-7 FPGA. Testing was performed both in proton irradiation and fault injection tests.

Ejemplares similares