Development of Integreted Electronics for Monolithic pixel detectors for the ALICE-ITS upgrade

This thesis is part of the ongoing studies for the upgrade of the Inner Tracking System (ITS) which is the innermost detector of ALICE (A Large Ion Collider Experiment) at CERN LHC. ALICE is a dedicated heavy-ion detector aiming to study and the characterize the Quark-Gluon Plasma (QGP). It will be undergone to an upgrade program to enable it to reach its physics objectives concerning the dynamics of the QGP after the Long Shutdown 2, foreseen 2018-2019. Indeed, an increase of the LHC instantaneous luminosity up to L = 6×1027cm−2s−1 for the Pb-Pb collisions will bring ALICE to accumulate 10 nb−1 for Pb-Pb collisions and to deal with an interaction rate of 50 kHz. In this way, a gain of 100 in statics will be possible in order to have access to rare probes at low and intermediate range of pT . The crucial limitations of current ALICE detector concern the overall material budget and a limited read-out rate capability. In particular, to overcome those limitations the ITS will be replaced with a new one with an higer spatial resolution together with an enhanced read-out rate capability. Actually, the ITS is the nearest detector to the interaction points and it deals with a large track densities, thus is essential to have a good impact parameter resolution. The new ITS will be made up of seven layers of Monolithic Active Pixel Sensors (MAPS). Indeed, the monolithic technology allows to reduce the overall material budget since one of the key feature of MAPS is the inte- gratation in the same silicon die of the sensor and the read-out electronics. The baseline for the pixel chip devolped for upgraded ITS is the ALPIDE pixel chip. It is implemented with the TowerJazz 0.18 um CMOS Imaging Sensor process since it offers a non standard MAPS with the quadruple well option which is essential to implement a full CMOS in-pixel circuitry an have a good resistance at the radiation damages of the ALICE environment. The sensor chip will measure 3 cm by 1.5 cm and contain about 500 000 pixels of about 28 by 28 microns. It consists of a pixel matrix and a chip periphery. The development of some key circuits located in the chip periphery will be treated in detail in this thesis. The chip periphery hosts those circuits which are necessary to link the ITS with an external Read-out Unit (RU) placed on a patch panel. These circuits are a Multipoint Low Voltage Differential Signaling (M-LVDS) transceiver and a pseudo-LVDS driver with pre-emphasis. They are respectively a slow speed and a high speed transmission circuit based on the LVDS standard transmission protocol. This standard allows for multipoint or point-to-point communications by ensuring a reduced power consumption and a good signal quality even at high data rate. The M-LVDS transceiver allows a bidirectional communication between the chips and/or the patch panel. It consists of a pseudo-LVDS driver and a LVDS receiver and it is in charge to broadcast the slow signals as the LHC 40 MHz clock, triggers and configuration settings. Thes driver is a three state buffer which allows a half-duplex bus topology in which only one driver at a time can transmit while every receiver in the line is receiving. Even if the driver works at 40 MHz (80 Mb/s), it has to drive a 6.5 m differential line at which multiple transceivers are connected. For this reason the driver strength of the MLVDS driver has to be high enough to overcome the bandwidth limitations due to the presence of the transmission line and the loads. The pseudo-LVDS driver is the high speed output circuit which sends out data from the chip periphery. The target speeds which will not limit the read-out of the full pixel chip are 1.2 Gb/s for the IB and 400 Mb/s for the OB. Therefore, these are the speed rates at which the driver has to transmit. Furthermore, it has to drive a full 5m/6.5m transmission line linking the detector with the patch panel. For this reason this high speed output is made up of a main driver and an ancillary pre-emphasis driver. Indeed, in the case in which data have to be broadcast at high speed and for long distances the pre-emphasis technique becomes essential to have a good transmission quality at the end of the lines. The last circuit that will be analized is a monitoring Analog to Digital Converter (ADC). This device controls some voltage levels inside the chip itself to guarantee the correct chip operation. The resolution foreseen for this device is 11-bit and the architecture takes advantage of the 2 conversion steps principle. All the circuits listed before are designed in the same 0.18 μm CMOS technology and operate from the same 1.8 V supply. All of them, with the exception of the ADC, will be integrated on the pixel chip prototypes. This thesis illustrates the design of the data transmission circuits and the development and characterization from simmulations and test results. Furthermore, the prelimary studies on this novel architecture are shown to demonstrate that the operating principle works.