Fixed-latency gigabit serial links in a Xilinx FPGA for the upgrade of the muon spectrometer at the ATLAS experiment

We present an implementation of fixed-latency gigabit serial links in a low-cost Xilinx field-programmable gate array. The implementation is targeted for a data packet router in the upgrade of the ATLAS muon spectrometer. The router serves as a packet switch. It handles up to 12 serial inputs at 4.8 Gbps from on-detector electronics and four 4.8-Gbps outputs to the trigger processing circuits. The input serial streams are deserialized and aligned to a common clock domain for NULL suppression and data packet forwarding. Gigabit transceivers are used in the processing, and a scheme is developed to maintain low and fixed-latency packet multiplexing through the router. We analyze the latency of the scheme and demonstrate its performance in a setup similar to that of the final detector arrangement.