Short-Strip ASIC (SSA): A 65nm silicon-strip readout ASIC for the Pixel-Strip (PS) module of the CMS Outer Tracker detector upgrade at HL-LHC

The Compact Muon Solenoid (CMS) experiment at CERN is foreseen to receive a substantial upgrade of the outer tracker detector and its front-end readout electronics, requiring higher granularity and readout bandwidth to handle the large number of pileup events in the High-Luminosity LHC. For this reason, the entire tracking system will be replaced with new detectors featuring higher radiation tolerance and ability to handle higher data rates and readout bandwidths. The possibility to identify particles with high transverse momentum (>2GeV/c) and provide primitives for the L1 trigger decision, was achieved by the adoption of double layer sensor modules, combining a pixel sensor with a strip one. Two different front-end ASICs were developed, the Short Strip ASIC (SSA) and the Macro-Pixel ASIC (MPA), in order to readout the sensors hits and to locally process and reduce the total output data flow with a compression factor of around 20. The SSA is the front-end ASIC responsible of reading-out the Short-Strip silicon sensor and to provide encoded information for the particle momentum discrimination. It is a 120-channel ASIC with double-threshold binary readout architecture, utilizing a quick hit cluster finding logic to provide encoded hit information for particle momentum discrimination to the Macro Pixel ASIC (MPA) at the bunch crossing rate of 40 MHz, while allowing the full sensor readout at a nominal average trigger rate of 1 MHz. To match the strict power requirement of 50 mW and the radiation tolerance up to a total ionizing dose of 200 Mrad, low power and radiation hardening techniques have been employed. The design and the implementation in a 65 nm CMOS technology of the first prototype ASIC that integrates all functionalities for system level operation is presented in this paper.