A Multi-Channel PCI Express Readout Board Proposal for the Pixel Upgrade at LHC

After having designed and commissioned the readout electronics currently implemented in the Insertable B-Layer, Layer 1 and Layer 2 of the ATLAS Pixel Detector (B-Layer and Disk readout electronics is under commissioning), we have designed a new readout electronic board looking primarily at the upgrade of the LHC Pixel Detectors. Two prototypes of a PCI Express board, namely Pixel_ROD, featuring all the minimal input-outputs interfaces to address the future front-end readout electronics, have already been fabricated and tested. The digital protocols used for the GBTx and for the RD53A chips have been investigated and we have been able to emulate physically a data acquisition chain interfacing with these components. The Pixel_ROD board might fit a variety of applications, from a test stand to qualify the RD53a chips that are currently under fabrication to a front-end physical emulator, designed via firmware, adaptable to any detector. As we have been working for years on the hardware and firmware of the IBL ReadOut Driver (ROD) card, we can also use this prototype board as a multi-channel FE-I4 emulator. An entire module of a Pixel Detector can be emulated by generating a very fast flux of data according to the desired protocol: FE-I4 compatible format for the current detector of ATLAS experiment and Aurora 64b/66b protocol for the next RD53A chip that will be used for ATLAS and CMS Pixel Detectors. The Pixel_ROD board in fact, features internal high-speed transceivers to interface easily from and to any other electronic board, electrically and/or optically, at the current desired bandwidth of the experiments for LHC. We have already started to carry out some tests, with the supervision of the ATLAS TDAQ collaboration, to interface with the FELIX card, either for data-acquisition or trigger functions, in view of any application towards the LHC phase-2 upgrade.