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Upgrade of the YARR DAQ system for the ATLAS Phase-II pixel detector readout chip
Yet Another Rapid Readout (YARR) is a DAQ system based on a software driven architecture using PCIe FPGA boards. It was designed for the readout of current generation ATLAS Pixel detector readout chips, which have a readout bandwidth of 160 Mb/s. YARR has been upgraded to accommodate the higher 5 Gb...
Autores principales: | , , , , , , |
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Lenguaje: | eng |
Publicado: |
SISSA
2018
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Materias: | |
Acceso en línea: | https://dx.doi.org/10.22323/1.313.0076 http://cds.cern.ch/record/2312402 |
_version_ | 1780958015719997440 |
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author | Whallon, Nikola Lazar Heim, Timon Garcia-Sciveres, Maurice Sautaux, Arnaud Oide, Hideyuki Potamianos, Karolos Hsu, Shih-Chieh |
author_facet | Whallon, Nikola Lazar Heim, Timon Garcia-Sciveres, Maurice Sautaux, Arnaud Oide, Hideyuki Potamianos, Karolos Hsu, Shih-Chieh |
author_sort | Whallon, Nikola Lazar |
collection | CERN |
description | Yet Another Rapid Readout (YARR) is a DAQ system based on a software driven architecture using PCIe FPGA boards. It was designed for the readout of current generation ATLAS Pixel detector readout chips, which have a readout bandwidth of 160 Mb/s. YARR has been upgraded to accommodate the higher 5 Gb/s bandwidth of the next generation readout chip in development by the RD53 collaboration for the Phase-II upgrade of the ATLAS and CMS detectors. The performance results of the migration to a new PCIe FPGA board, the PLDA XpressK7, will be presented. |
id | oai-inspirehep.net-1665034 |
institution | Organización Europea para la Investigación Nuclear |
language | eng |
publishDate | 2018 |
publisher | SISSA |
record_format | invenio |
spelling | oai-inspirehep.net-16650342019-10-15T15:20:48Zdoi:10.22323/1.313.0076http://cds.cern.ch/record/2312402engWhallon, Nikola LazarHeim, TimonGarcia-Sciveres, MauriceSautaux, ArnaudOide, HideyukiPotamianos, KarolosHsu, Shih-ChiehUpgrade of the YARR DAQ system for the ATLAS Phase-II pixel detector readout chipDetectors and Experimental TechniquesYet Another Rapid Readout (YARR) is a DAQ system based on a software driven architecture using PCIe FPGA boards. It was designed for the readout of current generation ATLAS Pixel detector readout chips, which have a readout bandwidth of 160 Mb/s. YARR has been upgraded to accommodate the higher 5 Gb/s bandwidth of the next generation readout chip in development by the RD53 collaboration for the Phase-II upgrade of the ATLAS and CMS detectors. The performance results of the migration to a new PCIe FPGA board, the PLDA XpressK7, will be presented.SISSAoai:inspirehep.net:16650342018 |
spellingShingle | Detectors and Experimental Techniques Whallon, Nikola Lazar Heim, Timon Garcia-Sciveres, Maurice Sautaux, Arnaud Oide, Hideyuki Potamianos, Karolos Hsu, Shih-Chieh Upgrade of the YARR DAQ system for the ATLAS Phase-II pixel detector readout chip |
title | Upgrade of the YARR DAQ system for the ATLAS Phase-II pixel detector readout chip |
title_full | Upgrade of the YARR DAQ system for the ATLAS Phase-II pixel detector readout chip |
title_fullStr | Upgrade of the YARR DAQ system for the ATLAS Phase-II pixel detector readout chip |
title_full_unstemmed | Upgrade of the YARR DAQ system for the ATLAS Phase-II pixel detector readout chip |
title_short | Upgrade of the YARR DAQ system for the ATLAS Phase-II pixel detector readout chip |
title_sort | upgrade of the yarr daq system for the atlas phase-ii pixel detector readout chip |
topic | Detectors and Experimental Techniques |
url | https://dx.doi.org/10.22323/1.313.0076 http://cds.cern.ch/record/2312402 |
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