Acceleration of an Particle Identification Algorithm Used for the LHCb Upgrade with the New Intel® Xeon®-FPGA

The LHCb experiment at the LHC will upgrade its detector by 2018/2019 to a ‘triggerless’ readout scheme, where all the readout electronics and several sub-detector parts will be replaced. The new readout electronics will be able to read out the detector at 40 MHz. This increases the data bandwidth from the detector down to the event filter farm to 40 Tb/s, which also has to be processed to select the interesting proton-to-proton collisions for later storage. The architecture of such a computing farm, which can process this amount of data as efficiently as possible, is a challenging task and several compute accelerator technologies are being considered for use inside the new event filter farm. In the high performance computing sector more and more FPGA compute accelerators are used to improve the compute performance and reduce the power consumption (e.g. in the Microsoft Catapult project and Bing search engine). Also for the LHCb upgrade, the usage of an experimental FPGA accelerated computing platform in the event building or in the event filter farm (trigger) is being considered and therefore tested. This platform from Intel® hosts a general Xeon® CPU and a high performance Arria® 10 FPGA inside a multi-chip package linked via a high speed and low latency link. On the FPGA an accelerator is implemented. The FPGA has cache-coherent memory access to the main memory of the server and can collaborate with the CPU. A computing intensive algorithm to reconstruct Cherenkov angles for the LHCb RICH particle identification was successfully ported to the Intel® Xeon®-FPGA platform and accelerated. The results show that the Intel® Xeon®-FPGA platforms, which are built in general for high performance computing, are also very interesting for the High Energy Physics community.