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MiniDAQ1: A Compact Data Acquisition System for GBT Readout over 10G Ethernet at LHCb
The LHCb experiment at CERN is undergoing a significant upgrade in anticipation of the increased luminosity that will be delivered by the LHC during Run 3 (starting in 2021). In order to allow efficient event selection in the new operating regime, the upgraded LHCb experiment will have to operate in...
Autores principales: | , , , , , , |
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Lenguaje: | eng |
Publicado: |
2018
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Materias: | |
Acceso en línea: | https://dx.doi.org/10.1007/978-981-13-1313-4_63 http://cds.cern.ch/record/2649804 |
_version_ | 1780960764546252800 |
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author | Durante, Paolo Cachemiche, Jean-Pierre Vouters, Guillaume Alessio, Federico Granado Cardoso, Luis Viana Barbosa, Joao Vitor Neufeld, Niko |
author_facet | Durante, Paolo Cachemiche, Jean-Pierre Vouters, Guillaume Alessio, Federico Granado Cardoso, Luis Viana Barbosa, Joao Vitor Neufeld, Niko |
author_sort | Durante, Paolo |
collection | CERN |
description | The LHCb experiment at CERN is undergoing a significant upgrade in anticipation of the increased luminosity that will be delivered by the LHC during Run 3 (starting in 2021). In order to allow efficient event selection in the new operating regime, the upgraded LHCb experiment will have to operate in continuous readout mode and deliver all 40 MHz of particle collisions directly to the software trigger. In addition to a completely new readout system, the front-end electronics for most sub-detectors are also to be redesigned in order to meet the necessary performance. Most front-end communication is based on a common ~5 Gb/s radiation-hard protocol developed at CERN, called GBT. MiniDAQ1 is a complete data-acquisition platform developed by the LHCb collaboration for reduced-scale tests of the new front-end electronics. The hardware includes 36 bidirectional optical links and a powerful FPGA in a small AMC form-factor. The FPGA implements data acquisition and synchronization, slow control and fast commands on all available GBT links, using a very flexible architecture allowing front-end designers to experiment with various configurations. The FPGA also implements a bidirectional 10G Ethernet network stack, in order to deliver the data produced by the front-ends to a computer network for final storage and analysis. An integrated single-board-computer runs the new control system that is also being developed for the upgrade, this allows MiniDAQ1 users to interactively configure and monitor the status of the entire readout chain, from the front-end up to the final output. |
id | oai-inspirehep.net-1687248 |
institution | Organización Europea para la Investigación Nuclear |
language | eng |
publishDate | 2018 |
record_format | invenio |
spelling | oai-inspirehep.net-16872482019-09-30T06:29:59Zdoi:10.1007/978-981-13-1313-4_63http://cds.cern.ch/record/2649804engDurante, PaoloCachemiche, Jean-PierreVouters, GuillaumeAlessio, FedericoGranado Cardoso, LuisViana Barbosa, Joao VitorNeufeld, NikoMiniDAQ1: A Compact Data Acquisition System for GBT Readout over 10G Ethernet at LHCbDetectors and Experimental TechniquesThe LHCb experiment at CERN is undergoing a significant upgrade in anticipation of the increased luminosity that will be delivered by the LHC during Run 3 (starting in 2021). In order to allow efficient event selection in the new operating regime, the upgraded LHCb experiment will have to operate in continuous readout mode and deliver all 40 MHz of particle collisions directly to the software trigger. In addition to a completely new readout system, the front-end electronics for most sub-detectors are also to be redesigned in order to meet the necessary performance. Most front-end communication is based on a common ~5 Gb/s radiation-hard protocol developed at CERN, called GBT. MiniDAQ1 is a complete data-acquisition platform developed by the LHCb collaboration for reduced-scale tests of the new front-end electronics. The hardware includes 36 bidirectional optical links and a powerful FPGA in a small AMC form-factor. The FPGA implements data acquisition and synchronization, slow control and fast commands on all available GBT links, using a very flexible architecture allowing front-end designers to experiment with various configurations. The FPGA also implements a bidirectional 10G Ethernet network stack, in order to deliver the data produced by the front-ends to a computer network for final storage and analysis. An integrated single-board-computer runs the new control system that is also being developed for the upgrade, this allows MiniDAQ1 users to interactively configure and monitor the status of the entire readout chain, from the front-end up to the final output.oai:inspirehep.net:16872482018 |
spellingShingle | Detectors and Experimental Techniques Durante, Paolo Cachemiche, Jean-Pierre Vouters, Guillaume Alessio, Federico Granado Cardoso, Luis Viana Barbosa, Joao Vitor Neufeld, Niko MiniDAQ1: A Compact Data Acquisition System for GBT Readout over 10G Ethernet at LHCb |
title | MiniDAQ1: A Compact Data Acquisition System for GBT Readout over 10G Ethernet at LHCb |
title_full | MiniDAQ1: A Compact Data Acquisition System for GBT Readout over 10G Ethernet at LHCb |
title_fullStr | MiniDAQ1: A Compact Data Acquisition System for GBT Readout over 10G Ethernet at LHCb |
title_full_unstemmed | MiniDAQ1: A Compact Data Acquisition System for GBT Readout over 10G Ethernet at LHCb |
title_short | MiniDAQ1: A Compact Data Acquisition System for GBT Readout over 10G Ethernet at LHCb |
title_sort | minidaq1: a compact data acquisition system for gbt readout over 10g ethernet at lhcb |
topic | Detectors and Experimental Techniques |
url | https://dx.doi.org/10.1007/978-981-13-1313-4_63 http://cds.cern.ch/record/2649804 |
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