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Proposal for a new ALICE CPV-HMPID front-end electronics topology

This paper presents the proposal of a new front-end readout electronics (RO) architecture for the ALICE Charged-particle Veto detector (CPV) located in PHOton Spectrometer (PHOS), and for the High Momentum particle IDentification detector (HMPID). With the upgrades in hardware typology and proposed...

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Detalles Bibliográficos
Autores principales: Seguna, Clive, Gatt, Edward, De Cataldo, Giacinto, Casha, Owen, Grech, Ivan
Lenguaje:eng
Publicado: 2017
Materias:
Acceso en línea:https://dx.doi.org/10.1109/PRIME.2017.7974135
http://cds.cern.ch/record/2659392
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author Seguna, Clive
Gatt, Edward
De Cataldo, Giacinto
Casha, Owen
Grech, Ivan
author_facet Seguna, Clive
Gatt, Edward
De Cataldo, Giacinto
Casha, Owen
Grech, Ivan
author_sort Seguna, Clive
collection CERN
description This paper presents the proposal of a new front-end readout electronics (RO) architecture for the ALICE Charged-particle Veto detector (CPV) located in PHOton Spectrometer (PHOS), and for the High Momentum particle IDentification detector (HMPID). With the upgrades in hardware typology and proposed new readout scheme in FPGA design, the RO system shall achieve at least five times the speed of the present front-end readout electronics. Design choices such as using the ALTERA Cyclone V GX FPGA, the topology for parallel readout of Dilogic cards and an upgrade in FPGA design interfaces will enable the RO electronics to reach an approximate interaction rate of 50 kHz. This paper presents the new system hardware as well as the preliminary prototype measurement results. This paper concludes with recommendations for other future planned updates in hardware schema.
id oai-inspirehep.net-1713287
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2017
record_format invenio
spelling oai-inspirehep.net-17132872019-09-30T06:29:59Zdoi:10.1109/PRIME.2017.7974135http://cds.cern.ch/record/2659392engSeguna, CliveGatt, EdwardDe Cataldo, GiacintoCasha, OwenGrech, IvanProposal for a new ALICE CPV-HMPID front-end electronics topologyDetectors and Experimental TechniquesDetectors and Experimental TechniquesThis paper presents the proposal of a new front-end readout electronics (RO) architecture for the ALICE Charged-particle Veto detector (CPV) located in PHOton Spectrometer (PHOS), and for the High Momentum particle IDentification detector (HMPID). With the upgrades in hardware typology and proposed new readout scheme in FPGA design, the RO system shall achieve at least five times the speed of the present front-end readout electronics. Design choices such as using the ALTERA Cyclone V GX FPGA, the topology for parallel readout of Dilogic cards and an upgrade in FPGA design interfaces will enable the RO electronics to reach an approximate interaction rate of 50 kHz. This paper presents the new system hardware as well as the preliminary prototype measurement results. This paper concludes with recommendations for other future planned updates in hardware schema.oai:inspirehep.net:17132872017
spellingShingle Detectors and Experimental Techniques
Detectors and Experimental Techniques
Seguna, Clive
Gatt, Edward
De Cataldo, Giacinto
Casha, Owen
Grech, Ivan
Proposal for a new ALICE CPV-HMPID front-end electronics topology
title Proposal for a new ALICE CPV-HMPID front-end electronics topology
title_full Proposal for a new ALICE CPV-HMPID front-end electronics topology
title_fullStr Proposal for a new ALICE CPV-HMPID front-end electronics topology
title_full_unstemmed Proposal for a new ALICE CPV-HMPID front-end electronics topology
title_short Proposal for a new ALICE CPV-HMPID front-end electronics topology
title_sort proposal for a new alice cpv-hmpid front-end electronics topology
topic Detectors and Experimental Techniques
Detectors and Experimental Techniques
url https://dx.doi.org/10.1109/PRIME.2017.7974135
http://cds.cern.ch/record/2659392
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