Effect of repetitive reset, temperature variation and frequency offset on the performance of PLL for the LHC experiments

The Large Hadron Collider (LHC) uses timing, trigger and control (TTC) system backbone to distribute the bunch clock and other critical timing signals to all the participating experiments. The clock signal is directly derived from the radio frequency (RF) driving the beams in the accelerator. The whole range of electronic systems from an ADC to high-speed transmission link works in synchronous to the clock signal and are sensitive to jitter. Throughout the clock distribution chain, high-frequency components increase the jitter. Multiple Phase-Locked Loops (PLLs) are used in the entire chain to maintain the jitter noise at a minimum level. Si5344 PLL by Silicon Labs is chosen as one of the candidate PLLs for jitter cleaning of the embedded clock in LHC gigabit serial link transmission. The article aims to highlight the qualification tests conducted to characterize the PLL component. Laboratory test setup is built to emulate the thermal variation of the LHC as in run-time condition. The present research study investigates the influence of temperature variation on PLL jitter-cleaning performance when operated in different configuration modes needed in TTC distribution chain. Stability of the PLL circuitry to lock correctly with repetitive reset assertion, power on/off cycle and marginal frequency swing about the LHC bunch clock mean frequency value is also studied.