The new octal amplifier–shaper–discriminator chip for the ATLAS MDT chambers at HL-LHC

In order to fully exploit the physics potential of the ATLAS experiment at the HL-LHC, the trigger rate of and maximum latency of the first-level trigger system will be increased to 1 MHz and 10μs , respectively. In addition, a new first-level muon track trigger with high momentum resolution based on the ATLAS precision Muon Drift-Tube (MDT) chambers will be employed which requires triggerless readout. The TDC ASICs of the current front-end electronics of the MDT chambers are incompatible with these requirements. The front-end boards, each with a TDC chip and three 8-channel amplifier–shaper–discriminator (ASD) chips have to be replaced. Therefore, a new octal ASD2 ASIC has been developed in modern 130 nm IBM/Global Foundries CMOS technology. The chip also contains a Wilkinson ADC to perform both time-over-threshold and signal charge measurement. The ASD design has been fully qualified for the serial production of 80000 chips for ATLAS. The performance in terms of signal rise time and channel uniformity significantly surpasses the one of the previous chip while keeping the power consumption constant. In addition to the characterization with test pulses, several chips have been mounted on the front-end boards and tested in a muon beam at the Gamma Irradiation Facility GIF++ at CERN up to high counting rates where the superior drift time and spatial resolution becomes evident.