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New LpGBT-FPGA IP: Simulation model and first implementation
High-speed links are commonly used in High Energy Physics experiments for data acquisition, trigger and timing distribution. For this reason, a radiation-hard link is being developed in order to match the increasing bandwidth demand of the backend electronics and computing systems. In this framework...
Autores principales: | , , , |
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Lenguaje: | eng |
Publicado: |
SISSA
2019
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Materias: | |
Acceso en línea: | https://dx.doi.org/10.22323/1.343.0059 http://cds.cern.ch/record/2710381 |
_version_ | 1780965196335939584 |
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author | Mendez, Julian Maxime Baron, Sophie Kulis, Szymon Fonseca, Jose |
author_facet | Mendez, Julian Maxime Baron, Sophie Kulis, Szymon Fonseca, Jose |
author_sort | Mendez, Julian Maxime |
collection | CERN |
description | High-speed links are commonly used in High Energy Physics experiments for data acquisition, trigger and timing distribution. For this reason, a radiation-hard link is being developed in order to match the increasing bandwidth demand of the backend electronics and computing systems. In this framework, the LpGBT - which is the evolution of the GBTx SERDES - is being designed and is foreseen to be installed in CMS and ATLAS for Phase-2 upgrades. The LpGBT-FPGA IP core is proposed to offer a backend counterpart of the LpGBT. This paper presents the IP architecture, the status of its development and future steps. |
id | oai-inspirehep.net-1747376 |
institution | Organización Europea para la Investigación Nuclear |
language | eng |
publishDate | 2019 |
publisher | SISSA |
record_format | invenio |
spelling | oai-inspirehep.net-17473762020-03-03T15:43:28Zdoi:10.22323/1.343.0059http://cds.cern.ch/record/2710381engMendez, Julian MaximeBaron, SophieKulis, SzymonFonseca, JoseNew LpGBT-FPGA IP: Simulation model and first implementationDetectors and Experimental TechniquesHigh-speed links are commonly used in High Energy Physics experiments for data acquisition, trigger and timing distribution. For this reason, a radiation-hard link is being developed in order to match the increasing bandwidth demand of the backend electronics and computing systems. In this framework, the LpGBT - which is the evolution of the GBTx SERDES - is being designed and is foreseen to be installed in CMS and ATLAS for Phase-2 upgrades. The LpGBT-FPGA IP core is proposed to offer a backend counterpart of the LpGBT. This paper presents the IP architecture, the status of its development and future steps.SISSAoai:inspirehep.net:17473762019 |
spellingShingle | Detectors and Experimental Techniques Mendez, Julian Maxime Baron, Sophie Kulis, Szymon Fonseca, Jose New LpGBT-FPGA IP: Simulation model and first implementation |
title | New LpGBT-FPGA IP: Simulation model and first implementation |
title_full | New LpGBT-FPGA IP: Simulation model and first implementation |
title_fullStr | New LpGBT-FPGA IP: Simulation model and first implementation |
title_full_unstemmed | New LpGBT-FPGA IP: Simulation model and first implementation |
title_short | New LpGBT-FPGA IP: Simulation model and first implementation |
title_sort | new lpgbt-fpga ip: simulation model and first implementation |
topic | Detectors and Experimental Techniques |
url | https://dx.doi.org/10.22323/1.343.0059 http://cds.cern.ch/record/2710381 |
work_keys_str_mv | AT mendezjulianmaxime newlpgbtfpgaipsimulationmodelandfirstimplementation AT baronsophie newlpgbtfpgaipsimulationmodelandfirstimplementation AT kulisszymon newlpgbtfpgaipsimulationmodelandfirstimplementation AT fonsecajose newlpgbtfpgaipsimulationmodelandfirstimplementation |