Cargando…

A High-resolution, Wide-range, Radiation-hard Clock Phase-shifter in a 65 nm CMOS Technology

The design and characterization results of a high-resolution phase-shifter are presented. The phase-shifter is designed with radiation hardening techniques and fabricated in 65 nm CMOS technology. The phase-shifter circuit can produce several output frequencies (40, 80, 160, 320, 640 or 1280 MHz) wi...

Descripción completa

Detalles Bibliográficos
Autores principales:	Kulis, Szymon, Yang, Dongxu, Ghong, Datao, Fonseca, Jose, Biereigel, Stefan, Ye, Jingbo, Moreira, Paulo
Lenguaje:	eng
Publicado:	IEEE 2019
Materias:	Detectors and Experimental Techniques
Acceso en línea:	https://dx.doi.org/10.23919/MIXDES.2019.8787202 http://cds.cern.ch/record/2729050

Ejemplares similares

A High-Resolution Clock Phase-Shifter in a 65 nm CMOS Technology
por: Yang, Dongxu, et al.
Publicado: (2018)

Radiation-Tolerant Digitally Controlled Ring Oscillator in 65-nm CMOS
por: Biereigel, Stefan, et al.
Publicado: (2022)

Radiation hard true single-phase-clock logic for high-speed circuits in 28 nm CMOS
por: Klekotko, A, et al.
Publicado: (2023)

Single-Event Effect Responses of Integrated Planar Inductors in 65-nm CMOS
por: Biereigel, Stefan, et al.
Publicado: (2021)

Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS
por: Biereigel, Stefan, et al.
Publicado: (2021)

A Low Noise Fault Tolerant Radiation Hardened 2.56 Gbps Clock-Data Recovery Circuit With High Speed Feed Forward Correction in 65 nm CMOS
por: Biereigel, Stefan, et al.
Publicado: (2019)

A Compact Low-Power Driver Array for VCSELs in 65-nm CMOS Technology
por: Zeng, Zhiyao, et al.
Publicado: (2017)

A Low Noise Fault Tolerant Radiation Hardened 2.56 Gbps Clock-Data Recovery Circuit with High Speed Feed Forward Correction in 65 nm CMOS
por: Prinzie, Jeffrey, et al.
Publicado: (2019)

CMOS 65nm engineering run
por: Re, Valerio
Publicado: (2018)

Radiation-hard ASICs for data transmission and clock distribution in High Energy Physics
por: Moreira, Paulo, et al.
Publicado: (2023)

A radiation-hard PLL for frequency multiplication with programmable input clock and phase-selectable output signals in 130 nm CMOS
por: Poltorak, K, et al.
Publicado: (2012)

Developments of two 4 × 10 Gb/s VCSEL array drivers in 65 nm CMOS for HEP experiments
por: Guo, D, et al.
Publicado: (2017)

Final design review of 65nm CMOS chips
por: Re, Valerio
Publicado: (2017)

Methods for clock signal characterization using FPGA resources
por: Biereigel, S, et al.
Publicado: (2020)

Radiation-tolerant all-digital clock generators for HEP applications
por: Biereigel, S, et al.
Publicado: (2023)

A 2.56-GHz SEU Radiation Hard $LC$ -Tank VCO for High-Speed Communication Links in 65-nm CMOS Technology
por: Prinzie, Jeffrey, et al.
Publicado: (2017)

Pixel front-end development in 65 nm CMOS technology
por: Havránek, M, et al.
Publicado: (2014)

Development of Radiation-hard Bandgap Reference and Temperature Sensor in CMOS 130 nm Technology
por: Kuczynska, Marika, et al.
Publicado: (2015)

CMOS-NEMS Copper Switches Monolithically Integrated Using a 65 nm CMOS Technology
por: Muñoz-Gamarra, Jose Luis, et al.
Publicado: (2016)

Characterization of a commercial 65 nm CMOS technology for SLHC applications
por: Bonacini, S, et al.
Publicado: (2012)

Optimization of a 65 nm CMOS imaging process for monolithic CMOS sensors for high energy physics
por: Rinella, G Aglieri, et al.
Publicado: (2023)

QTIA, a 2.5 or 10 Gbps 4-channel array optical receiver ASIC in a 65 nm CMOS technology
por: Sun, H., et al.
Publicado: (2021)

65 nm CMOS analog front-end for pixel detectors at the HL-LHC
por: Gaioni, L, et al.
Publicado: (2016)

Digital Pixel Test Structures implemented in a 65 nm CMOS process
por: Rinella, Gianluca Aglieri, et al.
Publicado: (2022)

Perspectives of 65 nm CMOS technologies for high performance front-end electronics
por: Traversi, G, et al.
Publicado: (2014)

Effects of Bias and Temperature on the Dose-Rate Sensitivity of 65-nm CMOS Transistors
por: Borghello, Giulio, et al.
Publicado: (2021)

Study of SEU Sensitivity of SRAM-Based Radiation Monitors in 65-nm CMOS
por: Wang, Jialei, et al.
Publicado: (2021)

Charge sensing properties of monolithic CMOS pixel sensors fabricated in a 65 nm technology
por: Bugiel, Szymon, et al.
Publicado: (2022)

Comparison of a 65 nm CMOS Ring- and LC-Oscillator Based PLL in Terms of TID and SEU Sensitivity
por: Prinzie, Jeffrey, et al.
Publicado: (2017)

28.6 A 78.5dB-SNDR radiation- and metastability-tolerant two-step split SAR ADC operating up to 75MS/s with 24.9mW power consumption in 65nm CMOS
por: Xu, Hongda, et al.
Publicado: (2017)

Dose-Rate Sensitivity of 65-nm MOSFETs Exposed to Ultrahigh Doses
por: Borghello, Giulio, et al.
Publicado: (2018)

A 4-fJ/Spike Artificial Neuron in 65 nm CMOS Technology
por: Sourikopoulos, Ilias, et al.
Publicado: (2017)

Low-Cutoff Frequency Reduction in Neural Amplifiers: Analysis and Implementation in CMOS 65 nm
por: Hashemi Noshahr, Fereidoon, et al.
Publicado: (2021)

An 8-channel programmable 80/160/320 Mbit/s radiation-hard phase-aligner circuit in 130-nm CMOS
por: Tavernier, F, et al.
Publicado: (2012)

Radiation hard DMAPS pixel sensors in 150 nm CMOS technology for operation at LHC
por: Barbero, M., et al.
Publicado: (2019)

Investigation of Scaling and Temperature Effects in Total Ionizing Dose (TID) Experiments in 65 nm CMOS
por: Chevas, Loukas, et al.
Publicado: (2018)

65-nm CMOS front-end channel for pixel readout in the HL-LHC radiation environment
por: Ratti, Lodovico, et al.
Publicado: (2017)

Characterization and Verification Environment for the RD53A Pixel Readout Chip in 65 nm CMOS
por: Vogt, M., et al.
Publicado: (2017)

Radiation Vulnerability in 65 nm CMOS I/O Transistors after Exposure to Grad Dose
por: Ding, Lili, et al.
Publicado: (2015)

Design of an analog monolithic pixel sensor prototype in TPSCo 65 nm CMOS imaging technology
por: Deng, W, et al.
Publicado: (2023)

Cannot write session to /tmp/vufind_sessions/sess_ha50d6ik3l6t12k7kml5proav1