GEM detector charge signals sequencer implementation for WEST experiment

This paper focuses on implementation of the charge signal sequencer in FPGA chip dedicated for GEM detector. First is described structure of GEM detector for WEST experiment developed by IPPLM and Warsaw University of Technology. Then the article explains why signal sequencer is needed in the new system and shortly presents how it works. It collects data from all detector channels and sends it out in unambiguous order to PC. It plays a big role in a data pipeline. Proper order of data improves parameters of the system, decreases the latency and simplifies computations on PC side. The article explains technical aspects of the implementation like architecture, blocks, dataflow or configuration features. In the end, there are presented results of the implementation.