Cargando…

Design and Test with Proton Beam of a 1.2 Gb/s Semi-custom Serialiser Implemented in 180 nm CMOS with SEU Mitigation by TMR

This contribution describes the design of a semi-custom serialiser in 180nm CMOS technology. The design is verified for SEU immunity and BER with 30MeV protons.

Detalles Bibliográficos
Autores principales:	Lupi, Matteo, Rinella, G Aglieri, Bonora, M, Hillemanns, H, Kim, D, Kugathasan, T, Lattuca, A, Mazza, G, Sielewicz, K M, Snoeys, W
Lenguaje:	eng
Publicado:	2017
Acceso en línea:	https://dx.doi.org/10.1109/RADECS.2017.8696110 http://cds.cern.ch/record/2713617

Ejemplares similares

Electrical and functional characterisation with single chips and module prototypes of the 1.2 Gb/s serial data link of the monolithic active pixel sensor for the upgrade of the ALICE Inner Tracking System
por: Bonora, Matthias, et al.
Publicado: (2017)

LAPA, a 5 Gb/s modular pseudo-LVDS driver in 180 nm CMOS with capacitively coupled pre-emphasis
por: Cardella, Roberto, et al.
Publicado: (2017)

A 1.2 Gb/s Data Transmission Unit in CMOS 0.18 μm technology for the ALICE Inner Tracking System front-end ASIC
por: Mazza, G, et al.
Publicado: (2017)

Experimental Methods and Results for the Evaluation of Triple Modular Redundancy SEU Mitigation Techniques with the Xilinx Kintex-7 FPGA
por: Sielewicz, Krzysztof M, et al.
Publicado: (2017)

Augmenting PODIO Serialisation
por: Fatemi Abhari, Ali
Publicado: (2018)

Charge collection properties of TowerJazz 180 nm CMOS Pixel Sensors in dependence of pixel geometries and bias parameters, studied using a dedicated test-vehicle: the Investigator chip
por: Aglieri Rinella, G., et al.
Publicado: (2020)

Study of SEU Sensitivity of SRAM-Based Radiation Monitors in 65-nm CMOS
por: Wang, Jialei, et al.
Publicado: (2021)

Design and characterization of an SEU-robust register in 130nm CMOS for application in HEP ASICs
por: Bonacini, S
Publicado: (2010)

Depleted Monolithic Active Pixel Sensors in the LFoundry 150 nm and TowerJazz 180 nm CMOS Technologies
por: Wang, T, et al.
Publicado: (2020)

Monolithic pixel development in 180 nm CMOS for the outer pixel layers in the ATLAS experiment
por: Kugathasan, Thanushan, et al.
Publicado: (2017)

Design of large scale sensors in 180 nm CMOS process modified for radiation tolerance
por: Flores Sanz de Acedo, L, et al.
Publicado: (2020)

Monolithic pixel development in TowerJazz 180 nm CMOS for the outer pixel layers in the ATLAS experiment
por: Berdalovic, I, et al.
Publicado: (2018)

Charge collection and efficiency measurements of the TJ-Monopix2 DMAPS in 180 nm CMOS technology
por: Bespin, Christian, et al.
Publicado: (2023)

High-speed bipolar phototransistors in a 180 nm CMOS process
por: Kostov, P., et al.
Publicado: (2013)

Comparison of a 65 nm CMOS Ring- and LC-Oscillator Based PLL in Terms of TID and SEU Sensitivity
por: Prinzie, Jeffrey, et al.
Publicado: (2017)

A process modification for CMOS monolithic active pixel sensors for enhanced depletion, timing performance and radiation tolerance
por: Snoeys, W, et al.
Publicado: (2017)

Design of a MEMS-Based Oscillator Using 180nm CMOS Technology
por: Roy, Sukanta, et al.
Publicado: (2016)

SEU characterization of commercial and custom-designed SRAMs based on 90 nm technology and below
por: Coronetti, Andrea, et al.
Publicado: (2020)

130nm TSMC / GF TID+SEU experience
por: Gonella, Laura, et al.
Publicado: (2020)

A 16-channel Silicon Strips Readout Chip in 180nm CMOS technology
por: Genat, Jean-François, et al.
Publicado: (2005)

Developments of two 4 × 10 Gb/s VCSEL array drivers in 65 nm CMOS for HEP experiments
por: Guo, D, et al.
Publicado: (2017)

10-Gb/s Distributed Amplifier-Based VCSEL Driver IC With ESD Protection in 130-nm CMOS
por: Zhang, Tao, et al.
Publicado: (2016)

A 10 Gb/s laser driver in 130 nm CMOS technology for high energy physics applications
por: Zhang, T, et al.
Publicado: (2015)

Results of the 2015 testbeam of a 180 nm AMS High-Voltage CMOS sensor prototype
por: Benoit, M., et al.
Publicado: (2016)

Resonant MEMS Pressure Sensor in 180 nm CMOS Technology Obtained by BEOL Isotropic Etching
por: Mata-Hernandez, Diana, et al.
Publicado: (2020)

Manufacturing and Characterization of Three-Axis Magnetic Sensors Using the Standard 180 nm CMOS Technology
por: Wu, Chi-Han, et al.
Publicado: (2021)

A 2.56-GHz SEU Radiation Hard $LC$ -Tank VCO for High-Speed Communication Links in 65-nm CMOS Technology
por: Prinzie, Jeffrey, et al.
Publicado: (2017)

Monolithic pixel development in TowerJazz 180 nm CMOS for the outer pixel layers in the ATLAS experiment
por: Pernegger, H
Publicado: (2019)

PNP PIN bipolar phototransistors for high-speed applications built in a 180 nm CMOS process
por: Kostov, P., et al.
Publicado: (2012)

TID and SEU performance of a commercial 013 $\mu$ m CMOS technology
por: Hänsler, Kurt, et al.
Publicado: (2004)

Meeting on TMR
por: Collective
Publicado: (1998)

Characterization of GEMINI, a 16-channels programmable readout interface for Triple-GEM detectors in 180nm CMOS
por: Mangiagalli, Luca, et al.
Publicado: (2019)

A Design of Adaptive Control and Communication Protocol for SWIPT System in 180 nm CMOS Process for Sensor Applications
por: Rehman, Muhammad Riaz Ur, et al.
Publicado: (2021)

Design of a Capacitance-to-Digital Converter Based on Iterative Delay-Chain Discharge in 180 nm CMOS Technology
por: Cicalini, Mattia, et al.
Publicado: (2021)

Development and characterization of a DMAPS chip in TowerJazz 180 nm technology for high radiation environments
por: Bespin, Christian, et al.
Publicado: (2022)

Design and readout architecture of a monolithic binary active pixel sensor in TPSCo 65 nm CMOS imaging technology
por: Cecconi, L, et al.
Publicado: (2023)

A Highly Accurate, Polynomial-Based Digital Temperature Compensation for Piezoresistive Pressure Sensor in 180 nm CMOS Technology
por: Ali, Imran, et al.
Publicado: (2020)

Progress in DMAPS developments and first tests of the Monopix2 chips in 150 nm LFoundry and 180 nm TowerJazz technology
por: Dingfelder, J, et al.
Publicado: (2022)

Design of an analog monolithic pixel sensor prototype in TPSCo 65 nm CMOS imaging technology
por: Deng, W, et al.
Publicado: (2023)

Digital Pixel Test Structures implemented in a 65 nm CMOS process
por: Rinella, Gianluca Aglieri, et al.
Publicado: (2022)

Cannot write session to /tmp/vufind_sessions/sess_8dceceg9i35nsurqmfao5vee6r