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CATIA: APD readout ASIC for CMS phase 2 ECAL electronics upgrade

The incoming LHC upgrade to HL‒LHC calls for a change of the ECAL front-end electronics design in order to maintain the present performance of the detector while facing a higher instantaneous luminosity and to optimize the timing resolution while using the existing crystals and APDs. The design of t...

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Detalles Bibliográficos
Autores principales: Gevin, Olivier, Baron, P, Dejardin, M, Guilloux, F
Lenguaje:eng
Publicado: SISSA 2020
Materias:
Acceso en línea:https://dx.doi.org/10.22323/1.370.0001
http://cds.cern.ch/record/2724948
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author Gevin, Olivier
Baron, P
Dejardin, M
Guilloux, F
author_facet Gevin, Olivier
Baron, P
Dejardin, M
Guilloux, F
author_sort Gevin, Olivier
collection CERN
description The incoming LHC upgrade to HL‒LHC calls for a change of the ECAL front-end electronics design in order to maintain the present performance of the detector while facing a higher instantaneous luminosity and to optimize the timing resolution while using the existing crystals and APDs. The design of the new front-end electronics is based on the cascading of two ASIC: a fast, dual gain trans-impedance amplifier designed in a 130 nm CMOS process (named CATIA) and a dual ADC designed in a 65 nm CMOS process. The latest test‒beam and laboratory test results of CATIA coupled with an ADC will be presented.
id oai-inspirehep.net-1792896
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2020
publisher SISSA
record_format invenio
spelling oai-inspirehep.net-17928962022-11-17T14:32:26Zdoi:10.22323/1.370.0001http://cds.cern.ch/record/2724948engGevin, OlivierBaron, PDejardin, MGuilloux, FCATIA: APD readout ASIC for CMS phase 2 ECAL electronics upgradeDetectors and Experimental TechniquesThe incoming LHC upgrade to HL‒LHC calls for a change of the ECAL front-end electronics design in order to maintain the present performance of the detector while facing a higher instantaneous luminosity and to optimize the timing resolution while using the existing crystals and APDs. The design of the new front-end electronics is based on the cascading of two ASIC: a fast, dual gain trans-impedance amplifier designed in a 130 nm CMOS process (named CATIA) and a dual ADC designed in a 65 nm CMOS process. The latest test‒beam and laboratory test results of CATIA coupled with an ADC will be presented.SISSAoai:inspirehep.net:17928962020
spellingShingle Detectors and Experimental Techniques
Gevin, Olivier
Baron, P
Dejardin, M
Guilloux, F
CATIA: APD readout ASIC for CMS phase 2 ECAL electronics upgrade
title CATIA: APD readout ASIC for CMS phase 2 ECAL electronics upgrade
title_full CATIA: APD readout ASIC for CMS phase 2 ECAL electronics upgrade
title_fullStr CATIA: APD readout ASIC for CMS phase 2 ECAL electronics upgrade
title_full_unstemmed CATIA: APD readout ASIC for CMS phase 2 ECAL electronics upgrade
title_short CATIA: APD readout ASIC for CMS phase 2 ECAL electronics upgrade
title_sort catia: apd readout asic for cms phase 2 ecal electronics upgrade
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.22323/1.370.0001
http://cds.cern.ch/record/2724948
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AT baronp catiaapdreadoutasicforcmsphase2ecalelectronicsupgrade
AT dejardinm catiaapdreadoutasicforcmsphase2ecalelectronicsupgrade
AT guillouxf catiaapdreadoutasicforcmsphase2ecalelectronicsupgrade