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Monolithic CMOS sensors for sub-nanosecond timing
In the ATTRACT project FASTPIX we investigate monolithic pixel sensors with small collection electrodes in CMOS technologies for fast signal collection and precise timing in the sub-nanosecond range. Deep submicron CMOS technologies allow tiny, sub-femtofarad collection electrodes, and large signal-...
Autores principales: | , , , , , , , , |
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Lenguaje: | eng |
Publicado: |
2020
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Materias: | |
Acceso en línea: | https://dx.doi.org/10.1016/j.nima.2020.164461 http://cds.cern.ch/record/2728013 |
_version_ | 1780966455209099264 |
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author | Kugathasan, Thanushan Ando, Taeko Dannheim, Dominik Etoh, Takeharu Goji Munker, Magdalena Pernegger, Heinz Rivetti, Angelo Shimonomura, Kazuhiro Snoeys, Walter |
author_facet | Kugathasan, Thanushan Ando, Taeko Dannheim, Dominik Etoh, Takeharu Goji Munker, Magdalena Pernegger, Heinz Rivetti, Angelo Shimonomura, Kazuhiro Snoeys, Walter |
author_sort | Kugathasan, Thanushan |
collection | CERN |
description | In the ATTRACT project FASTPIX we investigate monolithic pixel sensors with small collection electrodes in CMOS technologies for fast signal collection and precise timing in the sub-nanosecond range. Deep submicron CMOS technologies allow tiny, sub-femtofarad collection electrodes, and large signal-to-noise ratios, essential for very precise timing. However, complex in-pixel circuits require some area, and one ofthe key limitations for precise timing is the longer drift time of signal charge generated near the pixel borders.Laying out the collection electrodes on a hexagonal grid and reducing the pixel pitch minimize the maximumdistance from the pixel border to the collection electrode. The electric field optimized with TCAD simulationspulls the signal charge away from the pixel border towards the collection electrode as fast as possible. Thisalso reduces charge sharing and maximizes the seed pixel signal hence reducing time-walk effects. Here thehexagonal geometry also contributes by limiting charge sharing at the pixel corners to only three pixels insteadof four. We reach pixel pitches down to about 8.7 μmbetween collection electrodes in this 180 nm technologyby placing only a minimum amount of circuitry in the pixel and the rest at the matrix periphery. Consumingseveral tens of micro-ampere per pixel from a 1.8 V supply offers a time jitter of only a few tens of picoseconds.This allows detailed characterization of the sensor timing performance in a prototype chip with several minimatrices of 64 pixels each with amplifier, comparator and digital readout and 4 additional pixels with analogbuffers. The aim is to prove sensor concepts before moving to a much finer line width technology and fullyintegrate the readout within the pixel at lower power consumption. |
id | oai-inspirehep.net-1811048 |
institution | Organización Europea para la Investigación Nuclear |
language | eng |
publishDate | 2020 |
record_format | invenio |
spelling | oai-inspirehep.net-18110482020-08-14T19:26:00Zdoi:10.1016/j.nima.2020.164461http://cds.cern.ch/record/2728013engKugathasan, ThanushanAndo, TaekoDannheim, DominikEtoh, Takeharu GojiMunker, MagdalenaPernegger, HeinzRivetti, AngeloShimonomura, KazuhiroSnoeys, WalterMonolithic CMOS sensors for sub-nanosecond timingDetectors and Experimental TechniquesIn the ATTRACT project FASTPIX we investigate monolithic pixel sensors with small collection electrodes in CMOS technologies for fast signal collection and precise timing in the sub-nanosecond range. Deep submicron CMOS technologies allow tiny, sub-femtofarad collection electrodes, and large signal-to-noise ratios, essential for very precise timing. However, complex in-pixel circuits require some area, and one ofthe key limitations for precise timing is the longer drift time of signal charge generated near the pixel borders.Laying out the collection electrodes on a hexagonal grid and reducing the pixel pitch minimize the maximumdistance from the pixel border to the collection electrode. The electric field optimized with TCAD simulationspulls the signal charge away from the pixel border towards the collection electrode as fast as possible. Thisalso reduces charge sharing and maximizes the seed pixel signal hence reducing time-walk effects. Here thehexagonal geometry also contributes by limiting charge sharing at the pixel corners to only three pixels insteadof four. We reach pixel pitches down to about 8.7 μmbetween collection electrodes in this 180 nm technologyby placing only a minimum amount of circuitry in the pixel and the rest at the matrix periphery. Consumingseveral tens of micro-ampere per pixel from a 1.8 V supply offers a time jitter of only a few tens of picoseconds.This allows detailed characterization of the sensor timing performance in a prototype chip with several minimatrices of 64 pixels each with amplifier, comparator and digital readout and 4 additional pixels with analogbuffers. The aim is to prove sensor concepts before moving to a much finer line width technology and fullyintegrate the readout within the pixel at lower power consumption.oai:inspirehep.net:18110482020 |
spellingShingle | Detectors and Experimental Techniques Kugathasan, Thanushan Ando, Taeko Dannheim, Dominik Etoh, Takeharu Goji Munker, Magdalena Pernegger, Heinz Rivetti, Angelo Shimonomura, Kazuhiro Snoeys, Walter Monolithic CMOS sensors for sub-nanosecond timing |
title | Monolithic CMOS sensors for sub-nanosecond timing |
title_full | Monolithic CMOS sensors for sub-nanosecond timing |
title_fullStr | Monolithic CMOS sensors for sub-nanosecond timing |
title_full_unstemmed | Monolithic CMOS sensors for sub-nanosecond timing |
title_short | Monolithic CMOS sensors for sub-nanosecond timing |
title_sort | monolithic cmos sensors for sub-nanosecond timing |
topic | Detectors and Experimental Techniques |
url | https://dx.doi.org/10.1016/j.nima.2020.164461 http://cds.cern.ch/record/2728013 |
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